计算机组织结构-computer organization

Chapter13

IntroductiontotheAlteraNiosIISoftProcessor3

1.1NiosIISystem.

1.2OverviewofNiosIIProcessorFeatures

1.3RegisterStructure

1.4AccessingMemoryandI/ODevices1

1.5Addressing

1.6Instructions

1.6.1LoadandStoreInstructions8

1.6.2ArithmeticInstructions9

1.6.3LogicInstructions10

1.6.4MoveInstructions11

1.6.5ComparisonInstructions11

1.6.6ShiftInstructions12

1.6.7RotateInstructions13

1.6.8BranchandJumpInstructions13

1.6.9SubroutineLinkageInstructions14

1.6.10ControlInstructions14

1.6.11CarryandOverflowDetection14

1.7AssemblerDirectives15

1.8ExampleProgram16

1.9ExceptionProcessing18

1.9.1SoftwareTrap18

1.9.2HardwareInterrupts18

1.9.3UnimplementedInstructions19

1.9.4DeterminingtheTypeofException19

1.9.5ExceptionProcessingExample19

1.10CacheMemory20

1.10.1CacheManagement20

1.10.2CacheBypassMethods21

1.11TightlyCoupledMemory21

Chapter222

IntroductiontotheAlteraSOPCBuilder22

2.1NiosIISystem22

2.2Altera^SOPCBuilder25

2.3IntegrationoftheNiosIISystemintoaQuartusIIProject33

2.3.1InstantiationoftheModuleGeneratedbytheSOPCBuilder33

2.3.2ProgrammingandConfiguration35

2.4RunningtheApplicationProgram35

2.4.1UsingaNiosIIAssemblyLanguageProgram36

Chapter340

AlteraMonitorProgram40

3.1InstallingtheAlteraMonitorProgram41

3.2StartingtheAlteraMonitorProgram43

3.3ConfiguringaNiosIISystem43

3.4ConfiguringaNiosIIProgram46

3.5CompilingandLoadingtheProgram47

3.6RunningtheProgram49

3.7UsingtheDisassemblyWindow50

3.8Singlestep52

3.9UsingBreakpoints52

3.10ExaminingandChangingRegisterValues55

3.11ExaminingandChangingMemoryContents57

3.12SettingaWatchExpression61

3.13ExaminingtheInstructionTrace63

3.14UsingConfigurationFiles64

3.15UsingtheTerminal65

3.16LoadingSamplePrograms67

3.17TheGDBServerPanel69

Chapter470

UsingtheSDRAMMemoryonAltera'sDE2Board70

4.1ExampleNiosIISystem71

4.2TheSDRAMInterface72

4.3UsingtheSOPCBuildertoGeneratetheNiosIISystem72

4.4IntegrationoftheNiosIISystemintotheQuartusIIProject76

4.5UsingaPhase-LockedLoop78

Chapter585

DebuggingofApplicationProgramsonAltera'sDE2Boards85

5.1ExampleSystem87

5.2DebuggingConcepts90

5.2.1ObservingaProblem90

5.2.2IdentifyingtheBug91

5.3CorrectiveAction91

5.4ExamplesofErrorsinanApplicationProgram92

5.4.1SyntaxErrors92

5.4.2TypingErrors92

5.4.3ErrorsinInterruptHandling92

5.4.4SubroutineLinkageErrors93

5.4.5ErrorsinAddressing94

5.5ConcludingReamarks94

Chapter695

LaboratoryExercise95

6.1Exercise1-——ASimpleComputerSystem95

6.1.1Parti95

6.1.2PartII96

6.1.3PartIII97

6.1.4PartIV97

6.1.5PartV97

6.1.6PartVI97

6.2Exercise2--Program-ControlledInput/Output98

6.2.1Part199

6.2.2PartII100

6.2.3PartIII100

6.2.4PartIV101

6.2.5PartV101

6.3Exercise3■--SubroutinesandStacks101

6.3.1Parti101

6.3.2PartII102

6.3.3PartIII102

6.3.4PartIV103

6.3.5PartV103

6.4Exercise4■一PollingandInterrupts103

6.4.1Parti105

6.4.2PartII107

6.4.3PartIII107

6.4.4PartIV107

2

6.4.5PartV108

6.5Exercise5•--BusCommunication109

6.5.1PartIIll

6.5.2PartII113

6.5.3PartIII114

6.6Exercise6•--BusControlandArbitration114

6.6.1Part1115

6.6.2PartII118

6.6.3PartIII119

6.7Exercise7--DMADataTransfer122

6.7.1Parti125

6.7.2PartII126

6.7.3PartIII127

6.7.4PartIV128

Chapter1

IntroductiontotheAlteraNiosIISoftProcessor

ThistutorialpresentsanintroductiontoAltera^NiosIIprocessor,whichisasoftprocessorthatcanbe

instantiatedonanAlteraFPGAdevice.ItdescribesthebasicarchitectureofNiosIIanditsinstructionset.The

NiosIIprocessoranditsassociatedmemoryandperipheralcomponentsareeasilyinstantiatedbyusing

Altera'sSOPCBuilderinconjuctionwiththeQuartusIIsoftware.

AfulldesciptionoftheNiosIIprocessorisprovidedintheNiosIIProcessorReferenceHandbook,

whichisavailableintheliteraturesectionoftheAlterawebsite.AnintroductiontotheSOPCBuilderisgiven

inthetutorialIntroductiontotheAlteraSOPCBuilder,whichcanbefoundintheUniversityProgramsection

ofthewebsite.

Contents:

1.1NiosIISystem

1.2OverviewofNiosIIProcessorFeatures

1.3RegisterStructure

1.4AccessingMemoryandI/ODevices

1.5Addressing

1.6InstructionSet

1.7AssemblerDirectives

1.8ExampleProgram

1.9ExceptionProcessing

1.10CacheMemory

1.11TightlyCoupledMemory

Altera'sNiosIIisasoftprocessor,definedinahardwaredescriptionlanguage,whichcanbe

implementedinAltera'sFPGAdevicesbyusingtheQuartusIICADsystem.Thistutorialprovidesabasic

introductiontotheNiosIIprocessor,intendedforauserwhowishestoimplementaNiosIIbasedsystemon

theAlteraDE2board.

3

1.1NiosIISystem

TheNiosIIprocessorcanbeusedwithavarietyofothercomponentstoformacompletesystem.These

componentsincludeanumberofstandardperipherals,butitisalsopossibletodefinecustomperipherals.

Altera'sDE2DevelopmentandEducationboardcontainsseveralcomponentsthatcanbeintegratedintoa

NiosIIsystem.AnexampleofsuchasystemisshowninFigure1-1.

Figure1-1.ANiosIIsystemimplementedontheDE2board.

TheNiosIIprocessorandtheinterfacesneededtoconnecttootherchipsontheDE2boardare

implementedintheCycloneIIFPGAchip.Thesecomponentsareinterconnectedbymeansofthe

interconnectionnetworkcalledtheAvalonSwitchFabric.MemoryblocksintheCycloneIIdevicecanbe

usedtoprovideanon-chipmemoryfortheNiosIIprocessor.Theycanbeconnectedtotheprocessoreither

directlyorthroughtheAvalonnetwork.TheSRAMandSDRAMmemorychipsontheDE2boardare

accessedthroughtheappropriateinterfaces.Input/outputinterfacesareinstantiatedtoprovideconnectionto

theI/Odevicesusedinthesystem.AspecialJTAGUARTinterfaceisusedtoconnecttothecircuitrythat

providesaUniversalSerialBus(USB)linktothehostcomputertowhichtheDE2boardisconnected.This

circuitryandtheassociatedsoftwareiscalledtheUSB-Blaster.Anothermodule,calledtheJTAGDebug

module,isprovidedtoallowthehostcomputertocontroltheNiosIIprocessor.

Itmakesitpossibletoperformoperationssuchasdownloadingprogramsintomemory,startingand

stoppingexecution,settingprogrambreakpoints,andcollectingreal-timeexecutiontracedata.

SinceallpartsoftheNiosIIsystemimplementedontheFPGAchiparedefinedbyusingahardware

descriptionlanguage,aknowledgeableusercouldwritesuchcodetoimplementanypartofthesystem.This

wouldbeanonnerousandtimeconsumingtask.Instead,onecanusetheSOPCBuildertoolintheQuartusII

softwaretoimplementadesiredsystemsimplybychoosingtherequiredcomponentsandspecifyingthe

parametersneededtomakeeachcomponentfittheoverallrequirementsofthesystem.

4

1.2OverviewofNiosIIProcessorFeatures

TheNiosIIprocessorhasanumberoffeaturesthatcanbeconfiguredbytheusertomeetthedemandsof

adesiredsystem.Theprocessorcanbeimplementedinthreedifferentconfigurations:

•NiosII/fisa"fast"versiondesignedforsuperiorperformance.Ithasthewidestscopeofconfiguration

optionsthatcanbeusedtooptimizetheprocessorfbrperformance.

•NiosII/sisa"standard”versionthatrequireslessresourcesinanFPGAdeviceasatrade-offfbr

reducedperformance.

•NiosIl/eisan"economy,'versionwhichrequirestheleastamountofFPGAresources,butalsohasthe

mostlimitedsetofuser-configurablefeatures.

TheNiosIIprocessorhasaReducedInstructionSetComputer(RISC)architecture.Itsarithmeticand

logicoperationsareperfbnnedonoperandsinthegeneralpurposeregisters.Thedataismovedbetweenthe

memoryandtheseregistersbymeansofLoadandStoreinstructions.

ThewordlengthoftheNiosIIprocessoris32bits.Allregistersare32bitslong.Byteaddressesina32-bit

wordareassignedinlittle-endianstyle,inwhichthelowerbyteaddressesareusedfbrthelesssignificant

bytes(therightmostbytes)oftheword.

TheNiosIIarchitectureusesseparateinstructionanddatabuses,whichisoftenreferredtoastheHarvard

architecture.

ANiosIIprocessormayoperateinthefollowingthreemodes:

•Supervisormode-allowstheprocessortoexecuteallinstructionsandperformallavailablefunctions.

Whentheprocessorisreset,itentersthismode.

•Usermode-theintentofthismodeistopreventexecutionofsomeinstructionsthatshouldbeusedfbr

systemspurposesonly.Someprocessorfeaturesarenotaccessibleinthismode.

•Debugmode-isusedbysoftwaredebuggingtoolstoimplementfeaturessuchasbreakpointsand

watchpoints.

ApplicationprogramscanberunineithertheUserorSupervisormodes.Presentlyavailableversionsof

theNiosIIprocessordonotsupporttheUsermode.

1.3RegisterStructure

TheNiosIIprocessorhasthirtytwo32-bitgeneralpurposeregisters,asshowninFigureI-2.Someof

theseregistersareintendedfbraspecificpurposeandhavespecialnamesthatarerecognizedbythe

Assembler.

•RegisterrOisreferredtoasthezeroregister.Italwayscontainstheconstant0.Thus,readingthis

registerreturnsthevalue0,whilewritingtoithasnoeffect.

•RegisterrlisusedbytheAssemblerasatemporaryregister;itshouldnotbereferencedinuser

programs

•Registersr24andr29areusedfbrprocessingofexceptions;theyarenotavailableinUsermode

•Registersr25andr30areusedexclusivelybytheJTAGDebugmodule

•Registersr27andr28arcusedtocontrolthestackusedbytheNiosIIprocessor

•Registerr31isusedtoholdthereturnaddresswhenasubroutineiscalled

5

RegisterNameFunction

r0zero0x00000000

rlatAssemblerTempoiary

r2

r3

r23

r24etExceptionTemporary0

r25brBreakpointTemporaiy(2)

r26gpGlobalPointer

r27spStackPointer

r28fpFramePointer

r29eaExceptionReturnAddress(1)

r30baBreakpointRetiiniAddress(2)

r31raReturnAddress

(1)TheregisterisnotavailableinUsermode

(2)TheresisterisusedexclusivelybytheJTAGDebugmodule

Figure1-2.GeneralPurposeregisters.

Therearesix32-bitcontrolregisters,asindicatedinFigure1-3.Thenamesgiveninthefigureare

recognizedbytheAssembler.Theseregistersareusedautomaticallyforcontrolpurposes.Theycanberead

andwrittentobyspecialinstructionsrdctlandwrctl,whichcanbeexecutedonlyinthesupendsormode.The

registersareusedasfollows:

•Registerctl()reflectstheoperatingstatusoftheprocessor.Onlytwobitsofthisregisteraremeaningful:

-UistheUser/Supervisormodebit;U=1fbrUsermode,whileU=0forSupervisormode.

-PIEistheprocessorinterrupt-enablebit.WhenPIE=1,theprocessormayacceptexternal

interrupts.WhenPIE=0,theprocessorignoresexternalinterrupts.

■Registerctllholdsasavedcopyofthestatusregisterduringexceptionprocessing.ThebitsEUand

EPIEarethesavedvaluesofthestatusbitsUandPIE.

•Registerctl2holdsasavedcopyofthestatusregisterduringdebugbreakprocessing.ThebitsBUand

BPIEarethesavedvaluesofthestatusbitsUandPIE.

•Registerctl3isusedtoenableindividualexternalinterrupts.Eachbitcorrespondstooneofthe

interruptsirqOtoirq31.Thevalueof1meansthattheinterruptisenabled,while0meansthatitis

disabled.

•Registerctl4indicateswhichinterruptsarepending.Thevalueofagivenbit,ct!4k,issetto1ifthe

interruptirqkisbothactiveandenabledbyhavingtheinterrupt-enablebit,ctl3k,setto1.

•Registerctl5holdsavaluethatuniquelyidentifiestheprocessorinamultiprocessorsystem.

RegisterName配1…bibo

ctlOstatusReseneduPIE

ctllestatiisResenedEUEPIE

ctl2bstatiisResenedBUBPIE

ctl3ienableIiitemipt-enablebits

ctl4ipendingPending-intemiptbits

ctl5cpnidUniqueprocessoridentifier

Figure1-3.Controlregisters.

1.4AccessingMemoryandI/ODevices

Figure1-4showshowaNiosIIprocessorcanaccessmemoryandI/Odevices.Forbestperfbnnance,the

NiosII/fprocessorcanincludebothinstructionanddatacaches.ThecachesareimplementedintheFPGA

6

memoryblocks.

Theirusageisoptionalandtheyarespecified(includingtheirsize)atthesystemgenerationtimeby

usingtheSOPCBuilder.TheNiosII/sversioncanhavetheinstructioncachebutnotthedatacache.TheNios

Il/eversionhasneitherinstructionnordatacache.

Anotherwaytogivetheprocessorfastaccesstotheon-chipmemoryisbyusingthetightlycoupled

memoryarrangement,inwhichcasetheprocessoraccessesthememoryviaadirectpathratherthanthrough

theAvalonnetwork.Accessestoatightlycoupledmemorybypassthecachememory.Therecanbeoneor

moretightlycoupledinstructionanddatamemories.Iftheinstructioncacheisnotincludedinasystem,then

theremustbeatleastonetightlycoupledmemoryprovidedforNiosIl/fandNiosII/sprocessors.On-chip

memorycanalsobeaccessedviatheAvalonnetwork.

OfTchipmemorydevices,suchasSRAM,SDRAM,andFlashmemorychipsareaccessedby

instantiatingtheappropriateinterfaces.Theinput/outputdevicesarememorymappedandcanbeaccessedas

memorylocations.

DataaccessestomemorylocationsandI/OinterfacesareperformedbymeansofLoadandStore

instructions,whichcausedatatobetransferredbetweenthememoryandgeneralpurposeregisters.

1.5Addressing

TheNiosIIprocessorissues32-bitaddresses.Thememoryspaceisbyte-addressable.Instructionscan

readandwritewords(32bits),halfwords(16bits),orbytes(8bits)ofdata.Readingorwritingtoanaddress

thatdoesnotcorrespondtoanexistingmemoryorI/Olocationproducesanundefinedresult.

Therearefiveaddressingmodesprovided:

7

•Immediatemode-a16-bitoperandisgivenexplicitlyintheinstruction.Thisvaluemaybesign

extendedtoproducea32-bitoperandininstructionsthatperformarithmeticoperations.

•Registermode-theoperandisinaprocessorregister

•Displacementmode-theeffectiveaddressoftheoperandisthesumofthecontentsofaregisteranda

signed16-bitdisplacementvaluegivenintheinstruction

•Registerindirectmode-theeffectiveaddressoftheoperandisthecontentsofaregisterspecifiedinthe

instruction.Thisisequivalenttothedisplacementmodewherethedisplacementvalueisequalto0.

•Absolutemode-a16-bitabsoluteaddressofanoperandcanbespecifiedbyusingthedisplacement

modewithregisterrOwhichalwayscontainsthevalue0.

1.6Instructions

AllNiosIIinstructionsare32-bitslong.Inadditiontomachineinstructionsthatareexecuteddirectlyby

theprocessor,theNiosIIinstructionsetincludesanumberofpseudoinstructionsthatcanbeusedinassembly

languageprograms.TheAssemblerreplaceseachpscudoinstructionbyoneormoremachineinstructions.

Figure1-5depictsthethreepossibleinstructionformats:I-type,R-typeandJ-type.Inallcasesthesix

bitsb5odenotetheOPcode.Theremainingbitsareusedtospecifyregisters,immediateoperands,or

extendedOPcodes.

•I-type-Five-bitfieldsAandBareusedtospecifygeneralpurposeregisters.A16-bitfieldIMMED16

providesimmediatedatawhichcanbesignextendedtoprovidea32-bitoperand.

•R-type-Five-bitfieldsA,BandCareusedtospecifygeneralpurposeregisters.An11-bitfieldOPXis

usedtoextendtheOPcode.

•J-type-A26-bitfieldIMMED26containsanunsignedimmediatevalue.Thisformatisusedonlyinthe

Callinstruction.

descriptionoftheinstructionset,includingthedetailsofhoweachinstructionisencoded,thereadershould

consulttheNiosIIProcessorReferenceHandbook.

1.6.1LoadandStoreInstructions

LoadandStoreinstructionsareusedtomovedatabetweenmemory(andI/Ointerfaces)andthegeneral

purposeregisters.TheyareofI-type.Forexample,theLoadWordinstruction

IdwrB,byte_offset(rA)

determinestheeffectiveaddressofamemorylocationasthesumofabyte_offsetvalueandthecontentsof

8

registerA.The16-bitbyteoffsetvalueissignextendedto32bits.The32-bitmemoryoperandisloadedinto

registerB.

Forinstance,assumethatthecontentsofregisterr4are126Oioandthebyte_offsetvalueis8Oio.Then,

theinstruction

Idwr3,80(r4)

loadsthe32-bitoperandatmemoryaddress134Oiointoregisterr3.

TheStoreWordinstructionhastheformat

stwrB,byte_offset(rA)

ItstoresthecontentsofregisterBintothememorylocationattheaddresscomputedasthesumofthe

byte_offsetvalueandthecontentsofregisterA.

ThereareLoadandStoreinstructionsthatuseoperandsthatareonly8or16bitslong.Theyarereferred

toasLoad/StoreByteandLoad/StoreHalfwordinstructions,respectively.SuchLoadinstructionsare:

•Idb(LoadByte)

•Idbu(LoadByteUnsigned)

•Idh(LoadHalfword)

•Idhu(LoadHalfwordUnsigned)

Whenashorteroperandisloadedintoa32-bitregister,itsvaluehastobeadjustedtofitintotheregister.

Thisisdonebysignextendingthe8-or16-bitvalueto32bitsintheIdbandIdhinstructions.IntheIdbuand

Idhuinstructionstheoperandiszeroextended.

ThecorrespondingStoreinstnictionsare:

•stb(StoreByte)

•sth(StoreHalfword)

ThestbinstructionstoresthelowbyteofregisterBintothememorybytespecifiedbytheeffective

address.ThesthinstructionstoresthelowhalfwordofregisterB.Inthiscasetheeffectiveaddressmustbe

halfwordaligned.

EachLoadandStoreinstructionhasaversionintendedfbraccessinglocationsinI/Odeviceinterfaces.

Theseinstructionsare:

•Idwio(LoadWordI/O)

•Idbio(LoadByteI/O)

•Idbuio(LoadByteUnsignedI/O)

•Idhio(LoadHalfwordI/O)

•Idhuio(LoadHalfwordUnsignedI/O)

•stwio(StoreWordI/O)

•stbio(StoreByteI/O)

•sthio(StoreHalfwordI/O)

Thedifferenceisthattheseinstructionsbypassthecache,ifoneexists.

1.6.2ArithmeticInstructions

Thearithmeticinstructionsoperateonthedatathatiseitherinthegeneralpurposeregistersorgivenas

animmediatevalueintheinstruction.TheseinstructionsareofR-typeorI-type,respectively.Theyinclude:

•add(AddRegisters)

・addi(AddImmediate)

■sub(SubtractRegisters)

•subi(SubtractImmediate)

•mul(Multiply)

•muli(MultiplyImmediate)

・div(Divide)

•divu(DivideUnsigned)

9

TheAddinstruction

addrC,rA,rB

addsthecontentsofregistersAandB,andplacesthesumintoregisterC.

TheAddImmediateinstruction

addirB,rA,IMMED16

addsthecontentsofregisterAandthesign-extended16-bitoperandgivenintheinstruction,andplacesthe

resultintoregisterB.Theadditionoperationintheseinstructionsisthesamefbrbothsignedandunsigned

operands;therearcnoconditionflagsthataresetbytheoperation.Thismeansthatwhenunsignedoperands

areadded,thecarryfromthemostsignificantbitpositionhastobedetectedbyexecutingaseparate

instruction.Similarly,whensignedoperandsareadded,thearithmeticoverflowhastobedetectedseparately.

Thedetectionoftheseconditionsisdiscussedinsection6.11.

TheSubtractinstruction

subrC,rA,rB

subtractsthecontentsofregisterBfromregisterA,andplacestheresultintoregisterC.Again,thecarryand

overflowdetectionhastobedonebyusingadditionalinstructions,asexplainedinsection6.11.

Theimmediateversion,subi,isapseudoinstructionimplementedas

addirB,rA,-IMMED16

TheMultiplyinstruction

mulrC,rA,rB

multipliesthecontentsofregistersAandB,andplacesthelow-order32bitsoftheproductintoregisterC.

Theoperandsaretreatedasunsignednumbers.Thecarryandoverflowdetectionhastobedonebyusing

additionalinstructions.Intheimmediateversion

mulirB,rA,IMMED16

the16-bitimmediateoperandissignextendedto32bits.

TheDivideinstruction

divrC,rA,rB

dividesthecontentsofregisterAbythecontentsofregisterBandplacestheintegerportionofthequotient

intoregisterC.Theoperandsaretreatedassignedintegers.Thedivuinstructionisperformedinthesame

wayexceptthattheoperandsaretreatedasunsignedintegers.

1.6.3LogicInstructions

ThelogicinstructionsprovidetheAND,OR,XOR,andNORoperations.Theyoperateondatathatis

eitherinthegeneralpurposeregistersorgivenasanimmediatevalueintheinstruction.Theseinstructionsare

ofR-typeor1-typc,respectively.

TheANDinstruction

andrC,rA,rB

performsabitwiselogicalANDofthecontentsofregistersAandB,andstorestheresultinregisterC.

Similarly,theinstructionsor,xorandnorperforintheOR,XORandNORoperations,respectively.

TheANDImmediateinstruction

andirB,rA,IMMED16

performsabitwiselogicalANDofthecontentsofregisterAandtheIMMED16operandwhichiszero-

extendedto32bits,andstorestheresultinregisterB.Similarly,theinstructionsori,xoriandnoriperfbnn

theOR,XORandNORoperations,respectively.

Itisalsopossibletousethe16-bitimmediateoperandasthe16high-orderbitsinthelogicoperations,in

whichcasethelow-order16bitsoftheoperandarezeros.Thisisaccomplishedwiththeinstructions:

•andhi(ANDHighImmediate)

10

■orhi(ORHighImmediate)

•xorhi(XORHighImmediate)

1.6.4MoveInstructions

TheMoveinstructionscopythecontentsofoneregisterintoanother,ortheyplaceanimmediatevalue

intoaregister.Theyarepseudoinstructionsimplementedbyusingotherinstructions.Theinstruction

movrC,rA

copiesthecontentsofregisterAintoregisterC.Itisimplementedas

addrC,rA,rO

TheMoveImmediateinstruction

movirB,IMMED16

signextendstheIMMED16valueto32bitsandloadsitintoregisterB.Itisimplementedas

addirB,rO,IMMED16

TheMoveUnsignedImmediateinstruction

movuirB,IMMED16

zeroextendstheIMMED16valueto32bitsandloadsitintoregisterB.Itisimplementedas

orirB,rO,IMMED16

TheMoveImmediateAddressinstruction

moviarB,LABEL

loadsa32-bitvaluethatcorrespondstotheaddressLABELintoregisterB.Itisimplementedas:

orhirB,rO,%hi(LABEL)

orirB,rB,%lo(LABEL)

The%hi(LABEL)and%lo(LABEL)aretheAssemblermacroswhichextractthehigh-order16bits

andthelow-order16bits,respectively,ofa32-bitvalueLABEL.Theorhiinstructionsetsthehigh-orderbits

ofregisterB,followedbytheoriinstructionwhichsetsthelow-orderbitsofB.Notethattwoinstructionsare

usedbecausethe1-typcfbnnatprovidesforonlya16-bitimmediateoperand.

1.6.5ComparisonInstructions

TheComparisoninstructionscomparethecontentsoftworegistersorthecontentsofaregisterandan

immediatevalue,andwriteeither1(iftrue)or0(iffalse)intotheresultregister.TheyareofR-typeorI-type,

respectively.Theseinstructionscorrespondtoth