《数字集成电路设计实验（fpga）》实验二十八-源代码

--Title:VGA彩条发生器--libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;--------------------------------------------------------------------entityexp23isport(Clk:instd_logic;--时钟信号Key:instd_logic;--模式选择HS,VS:bufferstd_logic;--行同步和场同步R,G,B:outstd_logic--颜色输出);endexp23;--------------------------------------------------------------------architecturebehaveofexp23issignalfclk,cclk:std_logic;signalmmd:std_logic_vector(1downto0);--modeselectsignalfs:std_logic_vector(3downto0);signalcc:std_logic_vector(4downto0);--HorizontalSynchronizationsignalll:std_logic_vector(8downto0);--VerticalSynchronizationsignalgrbx:std_logic_vector(2downto0);--horizontalstripofXsignalgrby:std_logic_vector(2downto0);--verticalstripofYsignalgrbp:std_logic_vector(2downto0);signaldelay:std_logic_vector(15downto0);beginB<=grbp(0)andHSandVS;R<=grbp(1)andHSandVS;G<=grbp(2)andHSandVS;process(Clk)--modeofstripgenerationbeginif(Clk'eventandClk='1')thenif(Key='0')thenif(delay<60000)thendelay<=delay+1;endif;elsedelay<="0000000000000000";endif;if(delay=10000andmmd<3)thenmmd<=mmd+1;elsif(mmd=3)thenmmd<="00";endif;endif;endprocess;process(mmd)begincasemmdiswhen"00"=>grbp<=grbx;--choosehorizontalstripwhen"01"=>grbp<=grby;--chooseverticalstripwhen"10"=>grbp<=grbxxorgrby;--choosetessellateddesignationwhenothers=>grbp<="000";endcase;endprocess;process(Clk)beginif(Clk'eventandClk='1')then--12MHzclocksignaldevidedby13if(fs=12)thenfs<="0000";elsefs<=fs+1;endif;endif;endprocess;fclk<=fs(3);process(fclk)beginif(fclk'eventandfclk='1')thenif(cc=29)thencc<="00000";elsecc<=cc+1;endif;endif;endprocess;cclk<=cc(4);process(cclk)beginif(cclk'eventandcclk='1')thenif(ll=481)thenll<="000000000";elsell<=ll+1;endif;endif;endprocess;process(Clk)beginif(Clk'eventandClk='1')thenif(cc>23)thenHS<='0';--horizontalsynchronizationelseHS<='1';endif;if(ll>479)thenVS<='0';--verticalsynchronizationelseVS<='1';endif;endif;endprocess;process(Clk)beginif(Clk'eventandClk='1')thenif(cc<3)thengrbx<="111";elsif(cc<6)thengrbx<="110";elsif(cc<9)thengrbx<="101";elsif(cc<12)thengrbx<="100";elsif(cc<15)thengrbx<="011";elsif(cc<18)thengrbx<="010";elsif(cc<21)thengrbx<="001";elsegrbx<="000";endif;endif;endprocess;process(Clk)beginif(Clk'eventandClk='1')thenif(ll<60)thengrby<="111";elsif(ll<120)thengrby<="110";elsif(ll<180)thengrby<="101";elsif(ll<240)thengrby<="100";elsif(ll<300)thengrby<="