第10章 用Verilog描述电路模块

用Verilog描述数字电路模块组合电路—多路选择器用逻辑运算符直接描述逻辑函数式MUX2_1选择器modulemux21_dataflow( inputa, inputb, inputsel, outputf); assignf=sel&a|~sel&b;endmodule用过程块描述行为modulemux21_behave( inputa, inputb, inputsel, outputregf); always@(*) begin if(sel) f=a; else f=b; endendmodule参数定义数据宽度modulemux21_uni#(parameterwidth=4)( input[width-1:0]a, input[width-1:0]b, inputsel, outputreg[width-1:0]f); always@(*) begin if(sel) f=a; else f=b; endendmodule组合电路—多路选择器MUX4_1选择器modulemux41_if( input[3:0]a, input[3:0]b, input[3:0]c, input[3:0]d, input[1:0]sel, outputreg[3:0]f); always@(*) begin if(sel==2'b00) f=a; elseif(sel==2'b01) f=b; elseif(sel==2'b10) f=c; else f=d; endendmodulemodulemux41_case( input[3:0]a, input[3:0]b, input[3:0]c, input[3:0]d, input[1:0]sel, outputreg[3:0]f); always@(*) begin case(sel) 2'b00:f=a; 2'b01:f=b; 2'b10:f=c; 2'b11:f=d; endcase endendmodule组合电路—译码器（1）二进制译码器enin[2:0]d[7:0]0xxx00000000100000000001100100000010101000000100101100001000110000010000110100100000111001000000111110000000moduledecode38_behave( inputen, input[2:0]in, outputreg[7:0]d);

wire[3:0]t;

assignt={en,in}; always@(*) begin

case(t) 4'b1000:d=8'b00000001; 4'b1001:d=8'b00000010; 4'b1010:d=8'b00000100; 4'b1011:d=8'b00001000; 4'b1100:d=8'b00010000; 4'b1101:d=8'b00100000; 4'b1110:d=8'b01000000; 4'b1111:d=8'b10000000; default:d=8'b00000000; endcase endendmodule组合电路—译码器（1）moduledecode38_behave1( inputen, input[2:0]in, outputreg[7:0]d); always@(*) begin

if(en)

begin

case(in) 3'b000:d=8'b00000001; 3'b001:d=8'b00000010; 3'b010:d=8'b00000100; 3'b011:d=8'b00001000; 3'b100:d=8'b00010000; 3'b101:d=8'b00100000; 3'b110:d=8'b01000000; 3'b111:d=8'b10000000; endcase

end

else

begin d=8'b000000000;

end endendmoduleenin[2:0]d[7:0]0xxx00000000100000000001100100000010101000000100101100001000110000010000110100100000111001000000111110000000二进制译码器组合电路—译码器（2）七段数码管显示译码器moduleseg47( input[3:0]bcd, outputreg[6:0]abcdefg); always@(*) begin

case(bcd) 4'b0000:abcdefg=7'b1111110; 4'b0001:abcdefg=7'b0110000; 4'b0010:abcdefg=7'b1101101; 4'b0011:abcdefg=7'b1111001; 4'b0100:abcdefg=7'b0110011; 4'b0101:abcdefg=7'b1011011; 4'b0110:abcdefg=7'b1011111; 4'b0111:abcdefg=7'b1110000; 4'b1000:abcdefg=7'b1111111; 4’b1001:abcdefg=7’b1111011; default:abcdefg=7'b1001111; endcase endendmodule共阴连接的4-7译码器组合电路—移位器dir功能示例0左移1右移moduleshifter( input[7:0]d, inputdir, outputreg[7:0]d_out); always@(*) begin if(dir) d_out={1'b0,d[7:1]}; else d_out={d[6:0],1'b0}; endendmodulemoduleshifter_n( input[7:0]d, inputdir, input[2:0]amt, outputreg[7:0]d_out); always@(*) begin if(dir) d_out=d>>amt; else d_out=d<<amt; endendmodule always@(*) begin if(dir) d_out=d>>1; else d_out=d<<1; end时序电路—锁存器和触发器锁存器moduled_latch( inputclk, inputd, outputregq); always@(clk,d) begin if(clk) q=d; endendmoduleD触发器moduledff( inputclk, inputd, outputregq); always@(posedgeclk) begin q<=d; endendmodule使用always过程块，使用没有else的if语句时序电路—锁存器和触发器带异步复位reset的D触发器带异步复位reset和同步使能en的D触发器moduledff_rst_en( inputclk, inputreset, inputen, inputd, outputregq); always@(posedgeclk,posedgereset) begin if(reset) q<=1'b0; elseif(en) q<=d; endendmodulemoduledff_rst( inputclk, inputreset, inputd, outputregq); always@(posedgeclk,posedgereset) begin if(reset) q<=1'b0; else q<=d; endendmodule时序电路—寄存器参数化通用寄存器modulereg_uni#(parameterwidth=8)( inputclk, inputreset, inputen, input[width-1:0]d, outputreg[width-1:0]q); always@(posedgeclk,posedgereset) begin if(reset) q<=0; elseif(en) q<=d; endendmodule带异步复位、同步使能的8-bit寄存器modulereg_rst_en( inputclk, inputreset, inputen, input[7:0]d, outputreg[7:0]q); always@(posedgeclk,posedgereset) begin if(reset) q<=8'b0; elseif(en) q<=d; endendmodule时序电路—移位寄存器基本移位寄存器moduleshift_reg_4bit( inputclk, inputrst, inputdin, outputregdout); reg[2:0]q; always@(posedgeclk,posedgerst) begin if(rst) begin q<=3'b0; dout<=1'b0; end else begin q[0]<=din; q[1]<=q[0]; q[2]<=q[1]; dout<=q[2]; end endendmodulemoduleshift_reg_4bit1( inputclk, inputrst, inputdin, outputdout); reg[3:0]q; wire[3:0]next_q; always@(posedgeclk,posedgerst) begin if(rst) q<=4'b0; else

q<=next_q; end

assignnext_q={q[2:0],din}; assigndout=q[3];endmodule双向移位寄存器CLK控制输入触发器输出LOADDIR1X00DL01DR其他XXmoduleshift_bidir( inputclk, inputrst, inputload, inputdir, inputdl, inputdr, input[3:0]d, output[3:0]q); reg[3:0]qt; always@(posedgeclk,posedgerst) begin if(rst) qt<=4'b0; else begin if(load) qt<=d; else begin if(dir) qt<={dr,qt[3:1]}; else qt<={qt[2:0],dl}; end end end assignq=qt;endmodule时序电路—计数器最直接的方法就是使用算术运算符，直接描述计数器的行为基本计数器modulecounter16( inputclk, inputrst, outputreg[3:0]cnt); always@(posedgeclk,posedgerst) begin if(rst) cnt<=4'b0; else cnt<=cnt+1'b1; endendmodule也可以把计数器中的寄存器和次态逻辑分开描述modulecounter16_1( inputclk, inputrst, outputreg[3:0]cnt); wire[3:0]next_cnt; always@(posedgeclk,posedgerst) begin if(rst) cnt<=4'b0; else cnt<=next_cnt; end assignnext_cnt=cnt+1'b1;endmodule时序电路—计数器模M计数器modulecounter10( inputclk, inputrst, outputreg[3:0]cnt); always@(posedgeclk,posedgerst) begin if(rst) cnt<=4'b0; else begin if(cnt==4'b1001) cnt<=4'b0; else cnt<=cnt+1'b1; end endendmodule描述模M计数器，每当时钟沿到来时，计数值增1，当计数到M-1时，计数值归0可以把寄存器和次态逻辑分开描述modulecounter10_1( inputclk, inputrst, outputreg[3:0]cnt); wire[3:0]next_cnt; always@(posedgeclk,posedgerst) begin if(rst) cnt<=4'b0; else cnt<=next_cnt; end assignnext_cnt=(cnt==4'b1001)?4'b0000:cnt+1'b1;endmodulemodulecounter7_bidir( inputclk, inputrst, inputdir, outputreg[2:0]cnt); always@(posedgeclk,posedgerst) begin if(rst) cnt<=3'b0; else begin if(dir) begin if(cnt==3'b110) cnt<=0; else cnt<=cnt+1'b1; end else begin if(cnt==3'b000) cnt<=3'b110; else cnt<=cnt-1'b1; end end endendmodule双向计数器直接描述计数器的行为modulecounter7_bidir1( inputclk, inputrst, inputdir, outputreg[2:0]cnt); wire[2:0]next_cnt,incr_cnt,decr_cnt; always@(posedgeclk,posedgerst) begin if(rst) cnt<=3'b0; else cnt<=next_cnt; end assignincr_cnt=(cnt==3'b110)?3'b0:cnt+1'b1; assigndecr_cnt=(cnt==3'b000)?3'b110:cnt-1'b1; assignnext_cnt=(dir==1'b0)?incr_cnt:decr_cnt;endmodule可以把寄存器和次态逻辑分开描述时序电路—分频器分频器通常用计数器来实现可以分为计数器模块和计数值的译码逻辑的描述modulefdiv10( inputclk, inputrst, outputfdiv_out); reg[3:0]q; always@(posedgeclk,negedgerst) begin if(!rst) q<=4'b0; else begin if(q==9) q<=0; else q<=q+1'b1; end end assignfdiv_out=(q==9)?1'b1:1'b0;endmodule分频比也可以定义为参数modulefdiv10_1( inputclk, inputrst, outputfdiv_out);

localparamM=10; reg[3:0]q; always@(posedgeclk,negedgerst) begin if(!rst) q<=4'b0; else begin if(q==M-1) q<=0; else q<=q+1'b1; end end assignfdiv_out=(q==M-1)?1'b1:1'b0;endmodule内部寄存器宽度和分频比参数化modulefdiv_uni#(parameter N=20, M=500000) //用参数声明寄存器宽度和分频比( inputclk, inputrst, outputfdiv_out); reg[N-1:0]q;

always@(posedgeclk,negedgerst) begin if(!rst) q<=0; else begin if(q==M-1) q<=0; else q<=q+1'b1; end end

assignfdiv_out=(q==M-1)?1'b1:1'b0;endmodule输出的相位和占空比modulefdiv9( inputclk, inputrst, outputregfdiv_out); reg[3:0]q;

always@(posedgeclk,negedgerst) begin if(!rst) q<=4'b0; else begin if(q==8) q<=0; else q<=q+1'b1; end end

always@(*) begin case(q) 4'b0110:fdiv_out=1'b1; 4'b0111:fdiv_out=1'b1; default:fdiv_out=1'b0; endcase endendmodule时序电路—序列信号发生器序列信号发生器通常用计数器来实现由计数器和输出译码器构成moduleseq_gen( inputclk, inputrst, outputregseq_out); reg[2:0]q; always@(posedgeclk,negedgerst) begin if(!rst) q<=3'b0; else begin if(q==6) q<=3'b0; else q<=q+1'b1; end end

always@(*) begin case(q) 3'b000:seq_out=1'b1; 3'b001:seq_out=1'b1; 3'b010:seq_out=1'b0; 3'b011:seq_out=1'b0; 3'b100:seq_out=1'b1; 3'b101:seq_out=1'b1; 3'b110:seq_out=1'b0; default:seq_out=1'b0; endcase endendmodule状态机描述状态机时，需要定义状态，描述构成状态机的几个模块状态通常用参数定义，也可以用本地参数定义#(parameterS0=2’b00,S1=2’b01,S2=2’b10,S3=2’b11)localparam[1:0]S0=2’b00,S1=2’b01,S2=2’b10,S3=2’b11;用两个或三个过程块来分别描述寄存器、次态逻辑和输出逻辑状态机序列信号发生器：用状态机实现0011的序列信号发生器moduleseq_sm#(parameter ST0=2'b00, ST1=2'b01, ST2=2'b10, ST3=2'b11)( inputclk, inputrst, outputregz); reg[1:0]q; //寄存器的输出，当前态 reg[1:0]next_q; //次态逻辑的输出，次态

always@(posedgeclk,negedgerst) begin if(!rst) q<=2'b0; else q<=next_q; end

always@(q) begin case(q) ST0:next_q=ST1; ST1:next_q=ST2; ST2:next_q=ST3; ST3:next_q=ST0; endcase end

always@(q) begin case(q) ST0:z=1'b0; ST1:z=1'b0; ST2:z=1'b1; ST3:z=1'b1; endcase endendmodulemoduleseq_sm#(parameter[1:0] ST0=0, ST1=1, ST2=2, ST3=3)( inputclk, inputrst, outputregz); reg[1:0]q; //寄存器的输出，当前态 reg[1:0]next_q; //次态逻辑的输出，次态

always@(posedgeclk,negedgerst) begin if(!rst) q<=2'b0; else q<=next_q; end always@(q) begin case(q) ST0:begin next_q=ST1; z=1'b0; end ST1:begin next_q=ST2; z=1'b0; end ST2:begin next_q=ST3; z=1'b1; end ST3:begin next_q=ST0; z=1'b1; end endcase end endmodule序列检测器：检测1101序列（Moore机）moduleseq_check( inputclk, inputrst, inputx, outputz); localparam[2:0] s0=3'b000, s1=3'b001, s2=3'b010, s3=3'b011, s4=3'b100;

reg[2:0]current_state,next_state; always@(posedgeclk,negedgerst) begin if(!rst) current_state<=s0; else current_state<=next_state; end always@(current_state,x) begin case(current_state) s0:begin if(x) next_state=s1; else next_state=s0; end s1:begin if(x) next_state=s2; else next_state=s0; end s2:begin if(!x) next_state=s3; else next_state=s2; end s3:begin if(x) next_state=s4; else next_state=s0; end s4:begin if(x) next_state=s1; else next_state=s0; end default: next_state=s0; endcase end assignz=(current_state==s4)?1'b1:1'b0;endmodule序列检测器：检测1101序列（Mealy机） always@(*) begin z=1'b0; case(current_state) s0:begin if(x) next_state=s1; else next_state=s0; end s1:begin if(x) next_state=s2; else next_state=s0; end s2:begin if(!x) next_state=s3; else next_state=s2; end s3:begin if(x)begin next_state=s0; z=1'b1; end else next_state=s0; end endcase endendmodulemoduleseq_check_mealy#(parameter s0=2'b00, s1=2'b01, s2=2'b10, s3=2'b11)( inputclk, inputrst, inputx, outputregz); reg[1:0]current_state,next_state; always@(posedgeclk,negedgerst) begin if(!rst) current_state<=s0; else current_state<=next_state; end状态机—交通灯控制器状态主路支路时间MG_BR绿灯红灯45sMY_BR黄灯红灯5sMR_BG红灯绿灯25sMR_BY红灯黄灯5smoduletraffic#(parameter t_mg_br=6'd45, t_my_br=6'd5, t_mr_bg=6'd25, t_mr_by=6'd5) //用参数定义各状态的通行时间( inputclk, inputrst, outputreg[2:0]m_light, //主路灯输出，从高位到低位为红、绿、黄 outputreg[2:0]b_light, //支路灯输出，从高位到低位为红、绿、黄 outputreg[5:0]count); //计时输出 //用本地参数定义各状态 Localparam mg_br=2'b00, my_br=2'b01, mr_bg=2'b10, mr_by=2'b11; reg[1:0]current_state,next_state; reg[5:0]count_next; //计数器的次态 wire[5:0]count_minus; wiretime_out; wiremg_br_done,my_br_done,mr_bg_done,mr_by_done; ass