基于Xilinx fpga的ddr2 控制器设计方法ppt课件

1、A Practical Guide to DDR2 Design with Spartan-3A DSP,Featuring ISE 9.2 and the Xilinx Spartan-3A DSP 1800A Starter Platform,2,Course Objectives,By the end of the day, you will Build a functioning DDR2 controller in hardware Know whats required to design your own board,3,Morning Agenda,Memory, FPGAs,

2、 and Memory Controllers Memory trends DDR2 signaling Xilinx FPGA memory controllers Memory Interface Generator (MIG) Lab 1 Generate a DDR2 controller core Real-world Design with a MIG DDR2 Controller Interface to the MIG controller Logically simulate Hardware debug Lunch Break,4,Afternoon Agenda,Lab

3、 2 Build and verify a DDR2 controller in hardware PCB Considerations FPGA pinout Factors impacting signal quality and crosstalk PCB simulation example for DDR2 Trace requirements Power Customizing and Verifying the MIG Results Pinout rules Pin-swapping Verifying a new design Lab 3 Analyze and Fix Cu

4、stomized MIG Controllers,A Practical Guide to DDR2 Design with Spartan-3A DSP,Memory, FPGAs, and Memory Controllers,6,Memory, FPGAs, and Memory Controllers,Memory, FPGAs, and Memory Controllers Memory trends DDR2 signaling Xilinx FPGA memory controllers Memory Interface Generator (MIG) Lab 1 Generat

5、e a DDR2 controller core Real-world Design with a MIG DDR2 Controller Interface to the MIG controller Logically simulate Hardware debug Lunch Break,7,The FPGA/Memory Interface,Memory interface success in an FPGA is dependent on many things FPGA fabric Controller Memory Clock PCB Layout Power Well co

6、ver all these topics today,PCB,Memory,Controller,FPGA,Termination,Power,Termination,Clock,8,DDR2 Interface Covered Today,FPGA Spartan-3A DSP XC3SD1800A Memory Micron DDR2 MT47H32M16 Controller Xilinx Memory Interface Generator (MIG) PCB/Power/ Terminations Avnet-designed Spartan-3A DSP 1800A Starter

7、 Platform,9,Why DDR2?,Compared to DDR-1 Less expensive More readily available Lower power Larger varieties On-die termination (ODT) Well show details on this later Differential strobes Compared to DDR-3 More mature Easier to get Better controller support,10,DRAM Market and Technology Trend,DDR2 is t

8、he prevalent architecture 2007-2009 DDR is still widely used (low end applications) DDR3 is the upcoming technology,Data Source: iSupply,DRAM Shipments by Memory Technology Type,0,1000,2000,3000,4000,5000,6000,7000,8000,2002,2003,2004,2005,2006,2007,2008,2009,Forecast Year,Units (Millions),DDR3,DDR2

9、,DDR,SDRAM,RDRAM,EDO,FP / EDO,Note: The DDR3 forecast seems very optimistic,Slide Courtesy Xilinx,11,DDR SDRAM Component Comparison,*Raw speed of memory device, NOT necessarily the speed the FPGA controller can run,12,Memory Organization,Organized as Banks Rows Columns Each needs addressing,Bank 0,B

10、ank 1,Bank 2,Bank 3,Row,Column,DDR2,13,Bank Management,Latency to open a row Latency to close a row,4 or 8 banks per memory device,Any 1 row per bank can be open,Other devices can have different rows open,Slide courtesy Xilinx,14,Bank Interleave,Left side has bank/row conflicts same row in bank - co

11、nflict! Right side shows banks changing, but no conflict Higher throughput with bank interleave,Conflicts (gaps for activate, precharge),No Conflicts (no gaps),Slide courtesy Xilinx,15,Row/Column Addressing,Interface on S3ADSPSK is 32Mx32 (128 MB or 1 Gbit) Two chips (each 32Mx16) Each chip consists

12、 of 4 banks Each bank has 8K rows and 1K columns Each memory location stores 16 bits 2 chips * 4 banks * 8K rows * 1K columns * 16 bits = 1Gbit Linear addressing requires 25 address bits Our interface has 15 total address bits 13 ADDRESS (A) and 2 BANK ADDRESS (BA) BA1:0 selects one of four banks A1

13、2:0 with RAS selects one of 8K rows in the bank A9:0 with CAS selects one of 1K columns in the row,16,Control Signals,Combination of RAS, CAS, and WE determine action RAS asserted = Open Row Bank Address and Row Address latched in CAS and WE asserted = Write Column address latched in Write enabled C

14、AS asserted = Read Column address latched in RAS and WE asserted = Close Row (PRECHARGE) Row deactivated 1 means asserted (which is active low),17,Read Example,RAS asserted opens row Latches bank and row addresses Bank 3 Row 0 x000C CAS asserted by itself identifies the operation as read Latches the

15、 column address Column 0 x0000 With row open, multiple reads can be performed by re-asserted CAS Column 0 x0008,.,18,Multiple Reads,Five subsequent reads from the same row shown Burst length for this example is 8 Each time CAS asserts, 8 words are read 40 total words are read in this diagram Close r

16、ow (Pre-charge) shown after reading RAS and WE simultaneously asserted,19,Write Example,RAS asserted opens row Latches bank and row addresses Bank 3 Row 0 x000C CAS and WE asserted together identifies the operation as write Latches the column address Column 0 x0000 With row open, multiple writes can

17、 be performed by re-asserted CAS and WE Column 0 x0008,.,20,Multiple Writes,Five subsequent writes from the same row shown Burst length for this example is 8 Each time CAS/WE assert, 8 words are written 40 total words are written in this diagram Close row (Pre-charge) shown after reading RAS and WE

18、simultaneously asserted,21,Data Interface,One strobe (DQS) per 8 bits of data (DQ) DQS is a local clock for each data byte Can be differential One mask (DM) per 8 bits of data (DQ) Selects which bytes are active during a write (byte enable) 32-bit interface has 32 DQ, 4 DQS, and 4 DM bits FPGA outpu

19、ts DQS center aligned to the data for a write FPGA receives DQS edge aligned from the memory on a read,DQS,DQ,DATA WRITE FPGA DDR2,DQS,DQ,DATA WRITE DDR2 FPGA,22,Clock,Differential CK and CK# One clock pair per DDR2 chip Since S3ADSPSK has 2 DDR2 chips, the FPGA outputs 2 clock pairs Address and con

20、trol signals are registered at every positive edge of CK DQ and DQS outputs from DDR2 aligned with clock DDR2 uses an internal Delay Locked Loop (DLL) DLL has both a minimum and maximum frequency DDR2 specifications based on operating within this frequency range (125 MHz to 533 MHz),23,On-Die Termin

21、ation,ODT = On-Die Termination Enables built in stub termination on DDR2s data interface Eliminates need for stub termination resistors on the DDR2 side for data Adjustable: 50, 75, or 150,24,FPGA Interface,CLK,CLK_EN,CS,ADDRESS,BANK ADDRESS,RAS,CAS,WE,DQ,DQS,DM,ODT,RST_DQS_DIV,FPGA,DDR2 SDRAM,25,Wh

22、y Do I Need a Controller?,Easier to interface to a controller than directly to the memory Manages multiple operations Initialization See the DDR2 datasheet excerpt Calibration Shift outgoing DQS by 90 degrees Shift incoming DQS by 90 degrees Refresh DRAMs Simplified interface 4 potential commands in

23、stead of 15 Initialize command to MIG controller spawns 13 commands to DDR2,Reduces the design effort,26,Memory Interface Generator (MIG),Free utility to create a custom FPGA/memory interface Based on real, working, tested hardware Documented in Xilinx Application Notes (XAPP) Customized outputs inc

24、lude RTL source for the memory controller in Verilog or VHDL Simulation testbench and support User Constraint File (UCF) Pinout specific for chosen FPGA device/package Logic block locations FPGA timing constraints Batch files for processing Run ISE tools in command line mode Convert to ISE Project N

25、avigator Project Timing analysis Documentation,27,MIG v2.0 Component Controllers,Fastest clock rate in fastest FPGA speed grade See ,28,MIG v2.0 DIMM Controllers,Fastest clock rate in fastest FPGA speed grade See ,29,Spartan-3/3A DDR2 Controller,Performance Up to 166 MHz / 333 Mbps in -5 Speed grade

26、 device 200 MHz specific implementation documented in XAPP458 133 MHz/266 Mbps in -4 Speed grade device Spartan-3A only supports left and right sides Data Width Based on total available pins Component Up to 72-bit in Spartan-3 Up to 64-bit in Spartan-3A/3AN/3ADSP DIMM 64- and 72-bit in Spartan-3 64-

27、bit in Spartan-3A/3AN/3ADSP DQ to DQS Ratio is 8:1 No built-in bank management for Spartan controllers Virtex-5 has 4-bank Least Recently Used option,30,Embedded Processor Controllers,Interface DDR2 to a MicroBlaze processor Embedded Development Kit (EDK) 9.2 Includes the Multi-Port Memory Controlle

28、r v3 (MPMC3) MIG used for the physical layer All MIG rules and constraints apply See Answer Record 29221 Still set XIL_ROUTE_ENABLE_DATA_CAPTURE Use script to include MIG UCF in MicroBlaze system UCF Verify design built correctly (see Lab 3),31,Where do I get MIG?,MIG is included with ISE Foundation

29、/WebPACK Part of CORE Generator Graphical User Interface (GUI) provides access to Core library Datasheets 3rd party contact information Available Xilinx Solution Records Must Install ISE IP update MIG v2.0 in ISE 9.2 IP Update 2 Get IP Updates at Find more information at WebPACK WebPACK is free! Web

30、PACK supports XC3SD1800A on S3ADSPSK ,32,MIG Documentation,MIG Users Guide (UG086) Xilinx Application Notes XAPP768c (Spartan DDR) XAPP454 (Spartan DDR2) XAPP458 (Spartan-3A Starter 200 MHz DDR2) XAPP858 (Virtex-5 DDR2) XAPP701 & XAPP702 (Virtex-4 DDR2 Direct Clocking) XAPP721 & XAPP723 (Virtex-4 DD

31、R2 SERDES) Virtex-5 ML561 Memory Interfaces Users Guide (UG199),33,MIG Design Flow With Project Navigator,.,Project Navigator,Core Generator,MIG,MIG Outputs,Integrate Design,Download Design to Hardware,create_ise.bat,A Practical Guide to DDR2 Design with Spartan-3A DSP,Lab 1 Generate a DDR2 Controll

32、er with MIG,35,Lab 1 Overview,Run COREGen Run MIG Configure controller Generate Convert to Project Navigator Review raw outputs HDL UCF Build scripts,Project Navigator,Core Generator,MIG,MIG Outputs,Integrate Design,Download Design to Hardware,36,Lab 1 Review,What are the benefits of using MIG? What

33、 is required to use Project Navigator with a MIG design? Other observations? Pinouts match our board? What else did you notice about the UCF? Properties match between ProjNav and command-line script?,A Practical Guide to DDR2 Design with Spartan-3A DSP,Real-world Design with a MIG DDR2 Controller,38

34、,Real-world Design with a MIG DDR2 Controller,Memory, FPGAs, and Memory Controllers Memory trends DDR2 signaling Xilinx FPGA memory controllers Memory Interface Generator (MIG) Lab 1 Generate a DDR2 controller core Real-world Design with a MIG DDR2 Controller Interface to the MIG controller Logicall

35、y simulate Hardware debug Lunch Break,39,MIG Output Block Diagram,Memory,MIG Outputs,Memory Controller,User Logic,FPGA,Clock,Clock Management,Calibration,.,40,User Logic Operating Modes,Initialize User instructs controller to set up the DDR2 for operation Controller programs DDR2 with operating para

36、meters Parameters established by user during MIG generation Write User instructs controller to write data to memory Controller writes the data to the DDR2 Read User instructs controller to read data from memory Controller reads the data from the DDR2 Refresh Controller tells user a refresh is needed

37、 User pauses while controller handles refresh,41,Clock Domains in the User Logic,90-degree phase of DDR2 clock Used for all data-related signals Generated by a DCM Referred to as CLK90 180-degree phase of DDR2 clock Used for all control-related signals Generated by negative edge of 0-phase clock Ref

38、erred to as CLK180 or Falling Edge CLK0 Why is this important? User logic controls interaction between domains User must manage multiple clocks and resets,42,User Interface Signals,Initialization Complete,Auto Refresh Request,Write Data,Write Mask,Address,Burst Done,Command,Read Data,Data Valid,Comm

39、and Acknowledge,Auto Refresh Done,User Logic,Controller,Clocks & Resets,Clocks & Resets,43,Initialize,Initialization Complete,Command,User Logic,Controller,Clocks & Resets,Clocks & Resets,44,How to Initialize,Wait for RST_90 and RST_180 to deassert Set USER_CMD to b010 on CLK180 for one clock Wait f

40、or INIT_DONE to assert Minimum of 200 s,45,Write,Write Data,Write Mask,Address,Burst Done,Command,Command Acknowledge,User Logic,Controller,Clocks & Resets,Clocks & Resets,46,How to Write,Set USER_CMD to b100 and Address on CLK180 Wait for USER_CMD_ACK Set the DATA and MASK on CLK90 A dataword is do

41、uble the memory interface Provide BURST_LENGTH/2 datawords (BL=8 4 words) Set the next address and data Assert BURST_DONE on CLK180 after the last address Deassert USER_CMD after BURST_DONE,47,Read,Address,Burst Done,Command,Read Data,Data Valid,Command Acknowledge,User Logic,Controller,Clocks & Res

42、ets,Clocks & Resets,48,How to Read,Set USER_CMD to b110 and Address on CLK180 Wait for USER_CMD_ACK Set the next address Assert BURST_DONE on CLK180 after the last address Deassert USER_CMD after BURST_DONE Watch for Data Valid to indicate when data is good (CLK90),49,Refresh,Auto Refresh Request,Au

43、to Refresh Done,User Logic,Controller,Clocks & Resets,Clocks & Resets,50,How to Refresh,At all times, check for auto refresh request (AR_REQ) in the CLK180 domain If AR_REQ, then do not start a new transaction Wait for AR_DONE (CLK180) Go back to what you were doing,51,User Logic Address,Starting ad

44、dress for burst DDR2 auto-increments address for burst Combines addresses for bank, row, and column (row) : (column) : (bank address) 32M x 32 example Address bus is 26 bits User_A25:13 is the Row Address User_A12:2 is the Column Address User_A1:0 is the Bank Address Why is Column Address 11 bits? 1

45、K columns per row only requires 10 bits,52,Column Address A10,Column address bit A10 is special PRECHARGE is the DDR2 “Close Row” command Deactivates current row Returns bank to the idle state Auto-PRECHARGE DDR2 automatically closes the row after the current operation MIG does not support auto-prec

46、harge, but still reserves A10 To set Auto-PRECHARGE, assert column address A10 What if a column needs 11 or more address bits? Rare, but if so, A10 gets skipped What if a column needs 9 or fewer address bits? Extra address bits added up to A10 32Mx32 has 11 column address bits A9:0 for the address A

47、10 reserved for user to create custom, auto-precharge logic,53,User Interface Commands,54,User Logic Interface - 32Mx32 Example,55,DDR2 SDRAM,Lut delay,FIFO,Lut delay,FIFO,Address, Command, & Control,Controller,User Interface,Write Datapath,LUT delay Calibration Monitor,Read Capture,User_output_data

48、,FPGA Clock,User_input_data,User_address,LUT delay select,User_command,User_burst_done,User_cmd_ack,User_data_mask,User_data_valid,DCM,Input_clock,Clocks all modules in fabric,DQS, DQ,DM,Spartan-3x FPGA,Spartan-3x Memory Interface Architecture,Slide courtesy Xilinx,.,56,System Reference Clock,MIG as

49、sumes this to be differential SYS_CLK and SYS_CLKb MIG assumes it to be the controller frequency User must connect the real system clock Single-ended clock is acceptable Differential has less jitter Can a DCM synthesize the proper frequency? Yes, if you account for jitter in timing calculations User

50、 must edit several MIG RTL files Shown in Lab 2,57,MIGs Two Output Designs,user_design For the user who wants to instantiate the MIG controller Top-level exposes all DDR2 external signals and User Logic interface No instantiation template provided example_design Adds a User Logic example Top-level o

51、nly exposes DDR2 external signals Adds wrapper layers to connect controller, calibration, clock management, and User Logic More practical starting point,58,example_design File Hierarchy,Memory controller User Logic Clock management Calibration,59,Logical Simulation,MIG generates logical simulation f

52、iles VHDL or Verilog testbench ModelSIM “do” file Micron memory model Assuming the Micron license agreement is checked Verilog only Newer versions available directly from Micron,60,Simulator Support,61,VHDL Options,Use a mixed-language simulator ModelSIM SE tested and supported by Xilinx Get 3rd par

53、ty VHDL models for the memory Not tested or supported by Xilinx Wait for ISE 10.1 to consider ISE Simulator,62,Hardware Debug,External logic analyzer Consider adding Agilent Soft Touch connectorless probes Invaluable for performing full-speed measurements External scope Probe directly at the memory

54、or FPGA Leave break-out vias exposed for BGAs on prototypes Critical for measuring signal integrity Embedded logic analyzer Extremely versatile and inexpensive option ChipScope Pro,63,Debug Logic Anywhere Within the FPGA,Identify logic that you need to debug and verify ChipScope Pro cores are placed

55、 directly within the logic and Function as “virtual test headers” Provide access any signal or node with the FPGA Debug at the system clock rate,Clock,Trigger 0,Trigger 1,Trigger 2,Trigger 3,Trigger Out,Memory Controller,Address,Data,Clock,ILA,Xilinx,Slide courtesy Xilinx,64,ChipScope in Spartan,Chi

56、pScope cores take up FPGA resources Consider using a larger FPGA in prototypes ChipScope logic must meet timing Limited to around 200 MHz for Spartan ChipScope must run faster than DDR2 to see double data rate DDR2 lower limit is 125 MHz Not practical to run ChipScope at 250 MHz Consider violating 1

57、25 MHz limit Run DDR2 at 50 MHz Run ChipScope at 100 MHz or 200 MHz See this in Lab 2 High-speed measurements need to be taken with a high-speed logic analyzer,LUNCH,A Practical Guide to DDR2 Design with Spartan-3A DSP,Lab 2 Build and verify a DDR2 controller in hardware,67,Lab 2 Overview,Modify the

58、 example design UCF to match the hardware Connect correct system clock Integrate new user logic Add ChipScope logic analyzer Build, download, and verify hardware,Project Navigator,Core Generator,MIG,MIG Outputs,Integrate Design,Download Design to Hardware,68,User Test Logic,Initialize the memory Write to fill the memory with incrementing pattern Read back the memory Handle auto-refresh when necessary,69,User Test Logic State Machine,Power On,Initialize Memory,Write,Read,Compare,70,Xilinx Spartan-3A DSP 1800A Starter