HV Process and Device高压工艺与器件.ppt

1、HV Process and Device,TD-HV,a,2,Agenda,High voltage product application HV Technology introduction HV voltage standard device 0.5um 5V/40V Mixed-signal Technology Features 0.5um 5V/40V Mixed-signal Design Flexibility 0.5um HV Mixed-Signal Process Flow Low dissipation output,CDMOS technology is creat

2、ed by merging LDMOS technology and CMOS technology. The majority of CDMOS processes are used for driver and power ICs. Adding BJT options, CDMOS will become BCD process.,CMOS High density digital and analog,CDMOS High density digital and analog; High Current output; Low dissipation output,a,9,High v

3、oltage Standard Device,Above 30v (LDMOS-lateral double diffusion MOS),a,10,40/25V (Vds/Vgs) device structure,Critical dimension: A: Channel length A affect the breakdown of punch through and Rdson B: Drift extension TO B, BV , Major C: TO to TO space C, BV, Major D: M1 overlap drain side TO D,BV, Mi

4、nor E: Poly overlap FOX E, BV, Minor Drain well to guard ring Provide the field isolation and reduce the latch up,a,11,0.5um 5V/40V Mixed-signal Technology Features,a,12,0.5um 5V/40V Mixed-signal Design Flexibility,a,13,0.5um HV Mixed-Signal Process Flow&Modules,If only normal/HVN,Dep. NMOS,Low Vt P

5、MOS,Dep. PMOS,a,14,0.5um HV Mixed-Signal Process Flow&Modules,PCM,Pad,Al3,Via2,Al2,Via1,Al1,P+ Plug,Contact,Low TC Poly2 Res.,ONO,High Res.,Low TC Res.,Poly2,N/PSD,Spacer,N/PLDD,Poly1 ,High Poly Res.,PIP CAP(ONO), is critical layer,a,15,Issue in development,HV NMOS Sub-threshold leakage,Sub-threshol

6、d leak in HV NMOS VT curve compared to 5v normal NMOS device. And from the graph, this device must has a parasitical NMOS parallel to HV NMOS, the parasitical NMOS VT is higher or smaller than HV NMOS.,a,16,Issue in development,Drain,Source,Gate,A: Normal HV NMOS device B&C: Parasitical device. Test condition: Vd=0.1v, Vsub=Vs=0v, Vg sweep from 0v to 5v,A,B,C,a,17,Issue in devel