第十四章IO环设计_1.ppt

1、第十四章,I/O设计及封装 （一）,Outlines,Basic structure of I/O cells Noise Cancellation ESD Protection Scheme I/O ring design Package Selection,Outlines,Basic structure of I/O cells Noise Cancellation ESD Protection Scheme I/O ring design Package Selection,Performance with Die, Package, Board,Three main killers

2、of performance Power supply noise Reference clock noise Signal integrity These challenges are relevant at the die, package, board and system level These challenges have existed at lower speeds but dramatically increase in high speeds,I/O Cell,I/O Cell Connect Core to Package,Supply Cell max current

3、Analog cell low voltage drop Digital cell Input: w/wo pull-up, pull-down, schmitt Trigger Output: driving strength, high speed, low noise Bi-directional input/output Special Cell power-cut I/O cell, Corner cell ,Category of I/O Cell,Basic Structure of I/O cells,Output Cell: Pre-driver Provide proper

4、 logic operation for IO circuits Level shift (e.g. 1.8v core voltage, 3.3v IO voltage for 0.18u process) Big post-driver IO buffer Provide big driving capability Provide ESD protection ability ESD protection Input Cell: Input buffer w/wo noise immunity (Schmitt Trigger ) W/wo pull up/down function E

5、SD protection,Basic Structure of I/O cell Cont.,Analog Input Cell: ESD protection without input resister Power (VDD/VSS): Big ESD protection cell for the I/O ring. Other cells: Filler cell: provide connection for the power/ground ring ESD protection Cell Decoupling cell,I/O Layout,Bonding pad,I/O fi

6、ller cell,As standard cell Height Power lines ESD Latch-up,Outlines,Basic structure of I/O cells Noise Cancellation ESD Protection Scheme I/O Ring Package Selection,Noise problem at High Speed I/O,Q: Can simply increase driver size to meet high speed requirement? A: No! Problems when output signal a

7、t high speed Ringing Bounce EMI,Noises Caused by Switching Activity on Output,Ringing,Ringing: Oscillation on the signals at the switching pins,Bounce,EMI: Electromagnetic Interference,EMI radiation is caused by High-frequency current but not by voltage perturbation.,EMI cont.,It is extremely danger

8、ous for a wireless system. The Ultimate noise source is in the chip. Controlling EMI at the chip level is becoming more critical. Special design in I/O cell and I/O ring,Noise Control I/O cell,Input with noise immunity circuit Output with slew rate control controlling Ringing, Bounce and EMI,Input N

9、oise Immunity,Schmitt Trigger circuit is commonly used to increase noise immunity for “low speed” input,Drawback: large delay on the input signal. Commonly used for slow serial modules, e.g. I2C, SPI,Output Noise Control Circuit,Slew rate control Ringing cancellation Bounce reduction EMI control,Rin

10、ging Cancellation and Bounce Reduction,Example circuit:,Ringing Cancellation cont.,Electromagnetic Interference Control,EMI radiation is caused by High-frequency current (I) not by voltage (V) perturbation. But the slew rate of the signal, dV/dt, reflect the high-frequency current. Controlling Signa

11、l Parameters, Rise and Fall times, to reduce high frequency harmonics of signals and controls spectrum density:,Bounce Reduction,Design bounce detect and cancellation circuit See the indication in Ringing Cancellation Reduce the number of I/Os which shares one pair of supplies More supplies for fast

12、 I/Os; less supplies for slow I/Os. Arrange the pin order to avoid switching at the same time Example: put the I/O cells for address signal and data signal alternatively as they will not switching at the same time. Separate power domains Separate the power domain according to pad functions. Analog b

13、ank, fast digital bank, slow digital bank . Add Decoupling capacitors between I/O cells add decoupling cap on unused empty space,Outlines,Basic structure of I/O cells Noise Cancellation ESD Protection Scheme I/O Ring Package Selection,Electro Static Discharge(ESD)Protection,IC was damaged due to Ele

14、ctrical Overstress,ESD Test Standard,Standard: JEDEC ESD standard Human Body Model (HBM) Machine Model (MM) Charge Device Model (CDM) Basic ESD requirement for products,ESD Protection,Reference:JAMES E. VINSON AND JUIN J. LIOU, SENIOR MEMBER, IEEE,Electrostatic Discharge in Semiconductor Devices: An

15、 Overview,Electrostatic Discharge in Semiconductor Devices: Protection Techniques, IEEE, 1998.,ESD Test Model,Human Body Model (HBM) Apply a large voltage,HBM test: Schematic and current,ESD Test Model - cont,Machine Model (MM) Example: test machine handler Apply big current,MM test: Schematic and c

16、urrent,ESD Test Model - cont,Charge Device Model (CDM) Charge accumulated inside of IC CDM is the most dangerous case to damager the IC,ESD Test Cases,I/O to power pins,ESD Test Cases cont.,Supply pins,ESD Test Cases - cont,IO pin-to-pin ESD test,ESD Protection Circuit,Concept: provide ESD paths (sh

17、ort-circuit path) in order to prevent the ESD current into internal circuit ESD Protection Scheme Input protection Output protection VDD to VSS ESD Protection Network,Global ESD Protection,Global ESD protection,Input ESD Protection Circuit,Two commonly used ESD protection circuits,Output ESD Protect

18、ion Circuit,Two commonly used ESD protection circuits,ESD Protection Network,VDD to VSS ESD path ESD voltage across VDD and VSS can be quickly discharged through the short-circuit path of turn-on NMOS,EDS cell or P/G cell,ESD Protection Network cont.,Provide ESD protection path between different pow

19、er/ground levels,Outlines,Basic structure of I/O cells Noise Cancellation ESD Protection Scheme I/O ring Package Selection,I/O Ring Connection,Make connection to power and ground lines Make a global ESD protect Design considerations: Die size impact Bounding ability ESD protection Noise immunity,Die Size,Pad-limited vs. core-limited,Die Size cont.,IO Cells with Fillers in In-line Bonding For core-limited Abutted IO Cells in Staggered Bonding For pad-limited,Bonding Capability,Package