理解DDR3及调试.ppt

1、DDR3 简介/调试,Kade Huang 2013.1,DDR/DDR2/DDR3比较,DDR2/DDR3 比较之PIN脚,DDR2 only contain Vref pin,DDR3 has Vrefca and Vrefdq which are used as command/address and data reference. DDR3 add a RESET# pin for asynchronous reset DDR3 add a ZQ PIN for internal ZQ calibration reference. ZQ Calibration command is u

2、sed to calibrate DRAM Ron & ODT values. For more detail, refer to Page 107 of DDR3 Standard(JESD79-3E).,DDR2/DDR3 比较之layout,DDR3 layout analyze,DDR3 之Write leveling,DDR3 之Write leveling 实现方式,DDR3 测试之读写分离,DDR3写操作时，DQS write preamble 在一个clk周期内先高后低，如下图所示：,DDR3 测试之读写分离(续),DDR3读操作时，DQS read preamble为一个cl

3、k周期的低电平，如下图所示：,DDR2/DDR3 比较之CWL,CWL：CAS write latency, its only defined in DDR3. In DDR2, WL = RL-1.,DDR 参数之CL,CL：CAS Latency 1. CAS latency is the delay, in clock cycles, between the internal Read command and availability of the first bit of output data. 2. programmable CAS Latency 5,6,7,8,9,10,11,

4、12,13 3. CL is only decided by DRAM . Ps, BL: Burst length,DDR 参数之tRCD,tRCD: RAS to CAS delay time(activate to read/write interval of SDRAM.) tRCD is only decided by DRAM.,DDR 参数之tRP,tRP: row precharge time 1.When need to read or write other row, the precharge command is used. tRP is the time that p

5、recharge to row. 2. tRP is only decided by DRAM.,DDR3 简单debug（以P2010为例）,tDSS,tDQSS,tDSH 时序不满足时 tDSS,tDQSS,tDSH定义如下：,tDSS,tDQSS,tDSH 时序不满足(续),下图为未使用WRLVL_EN功能波形，tDSS不满足要求,tDSS,tDQSS,tDSH 时序不满足(续),使用DDR3 WRLVL_EN后tDSS满足要求，波形如下：,DQ读写波形有较大overshoot,如下图，当写时DQS，DQ上存在较大的振铃。 此时DRAM端ODT设置为120ohm.,DQ写波形有较大overshoot(续),将DRAM测ODT修改为60ohm后测