CH10_阶层式设计.pptx

1、1,階層式設計,第十章,儒林圖書公司 TB061,VHDL數位電路設計實務教本 使用Quartus II,方塊(Block)敘述,2,Block主要是將同一電路中某一功能的電路以方塊敘述劃分起來，形成一個獨立的電路模組，最後將這些獨立模組組合起來構成我們的電路，模組化的設計方式可以使得系統的維護性和偵錯性大為提高。,Block方塊敘述的語法如下：,方塊(Block)敘述 Example：全加器設計,3,方塊(Block)敘述 Example：八對一多工器設計,4,library IEEE; use IEEE.STD_LOGIC_1164.all; entity MUX8_1b is port

2、( S : IN STD_LOGIC_VECTOR(2 downto 0); D0,D1,D2,D3,D4,D5,D6,D7: IN STD_LOGIC; Y: OUT STD_LOGIC); end MUX8_1b; architecture a of MUX8_1b is SIGNAL Y1,Y2:STD_LOGIC; begin MUX4TO1_1:BLOCK BEGIN Y1=(D0 AND (NOT S(1) AND (NOT S(0) OR (D1 AND (NOT S(1) AND S(0) OR (D2 AND S(1) AND (NOT S(0) OR (D3 AND S(1

3、) AND S(0); END BLOCK MUX4TO1_1;,MUX4TO1_2:BLOCKBEGIN Y2=(D4 AND (NOT S(1) AND (NOT S(0) OR (D5 AND (NOT S(1) AND S(0) OR (D6 AND S(1) AND (NOT S(0) OR (D7 AND S(1) AND S(0); END BLOCK MUX4TO1_2; MUX2TO1:BLOCK BEGIN Y=(Y1 AND not S(2) OR (Y2 AND S(2); END BLOCK MUX2TO1; end a;,Hierarchical design: C

4、omponent 與Port Map,5,Component的功能能夠協助我們作元件資料庫的設計，它與Port Map結合可以讓我們利用現有的component像堆積木一般累積出複雜的電路。,FA1: full_adder PORT MAP (Cin, a0, b0, S0, t1);,位置對應表示式 (must match the port order),FA1: full_adder PORT MAP (Cin=x, a0=y, b0=z, S0=Sum, t1=Carry);,名稱對應表示式: signal = port_name,Port Map腳位設定的方式如下:,Component

5、 與Port Map,6,Component 與Port Map:Example:四對一多工器描述(component),7,library IEEE; use IEEE.STD_LOGIC_1164.all; ENTITY mux4_1 IS PORT ( D0,D1,D2,D3 ,S1,S0 : IN STD_LOGIC; Y : OUT STD_LOGIC); END mux4_1 ; ARCHITECTURE a OF mux4_1 IS BEGIN Y=(D0 and (not S1)and (not S0) or (D1 and (not S1)and S0) or (D2 and

6、 S1 and (not S0) or (D3 and S1 and S0) ; END a;,Component 與Port Map: 利用四對一多工器的component建立十六對一多工器,8,ARCHITECTURE a OF mux16to1c IS component mux4_1 port ( d0,d1,d2,d3, S1,S0 :in std_logic; Y:out std_logic ); end component; signal m :std_logic_vector(0 to 3); BEGIN mux1:mux4_1 port map(d(0),d(1),d(2),

7、d(3),S(1),S(0),m(0); mux2:mux4_1 port map(d(4),d(5),d(6),d(7),S(1),S(0),m(1); mux3:mux4_1 port map(d(8),d(9),d(10),d(11),S(1),S(0),m(2); mux4:mux4_1 port map(d(12),d(13),d(14),d(15),S(1),S(0),m(3); mux5:mux4_1 port map(m(0),m(1),m(2),m(3),S(3),S(2),Y); END a;,Component 與Port Map:全加器電路設計,9,ARCHITECTU

8、RE a OF fulladder IS component halfadder port ( a,b :in std_logic; s,c : out std_logic ); end component; component or_2 port ( a,b :in std_logic; c :out std_logic ); end component; signal s1,s2,s3 :std_logic; BEGIN U1:halfadder port map(x,y,s1,s3); U2:halfadder port map(s1,z,sum,s2); U3:or_2 port ma

9、p(s2,s3,carry); END a;,Component declaration name,Component Instance,Component 與Port Map:上數計數器,10,architecture a of counter2 is component Tflip_flop port( ck: in bit; q: out bit); end component; component inverter port( a: in bit; y: out bit); end component; signal ff0, ff1, inv_ff0 : bit; begin IC1

10、: Tflip_flop port map(ck= clock, q = ff0 ); IC2: inverter port map( a= ff0, y = inv_ff0); IC3: Tflip_flop port map( ck= inv_ff0, q = ff1); q0 = ff0; q1 = ff1; end a;,11,Component 與Port Map:全加器架構,Sum(x,y,z) =(1,2,4,7),C(x,y,z) = (3,5,6,7),architecture a of comb_add is component OR_4v PORT( A,B,c,d:in

11、 std_logic; Z :out std_logic); end component; component de3to8 PORT( s0,s1,s2:in std_logic; m0,m1,m2,m3,m4,m5,m6,m7:out std_logic); end component;,signal n0,n1,n2,n3,n4,n5,n6,n7:std_logic; begin ic1:OR_4v port map(a=n1,b=n2,c=n4,d=n7,z=Sum); ic2:OR_4v port map(a=n3,b=n5,c=n6,d=n7,z=Carry); ic3:de3to

12、8 port map(s0=in1,s1=in2,s2=in3,m0=open,m1=n1,m2=n2, m3=n3,m4=n4,m5=n5,m6=open,m7=n7); end a;,Component 與Port Map:暫存器,12,Architecture a of REGH_4 is component AND_2 PORT( A,B:in std_logic; Z :out std_logic); end component; component DFF_V PORT( D,CLK : IN std_logic; Q : OUT std_logic ); end componen

13、t; signal int_clk : std_logic; begin IC0 : dff_v port map ( d0, int_clk, q0 ); IC1 : dff_v port map ( d1, int_clk, q1 ); IC2 : dff_v port map ( d2, int_clk, q2 ); IC3 : dff_v port map ( d3, int_clk, q3 ); IC4 : and_2 port map ( en, clk, int_clk ); end a;,Component 與Port Map:可作串、並列輸入，並列輸出的移位暫存器,13,AR

14、CHITECTURE Structure OF PISO_shift4 IS COMPONENT muxdff PORT ( D0, D1, Sel, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC ) ; END COMPONENT ; BEGIN IC3: muxdff PORT MAP ( serial_in, Paraller_in(3), Load, Clock, Q(3) ) ; IC2: muxdff PORT MAP ( Q(3), Paraller_in(2), Load, Clock, Q(2) ) ; IC1: muxdff PORT M

15、AP ( Q(2), Paraller_in(1), Load, Clock, Q(1) ) ; IC0: muxdff PORT MAP ( Q(1), Paraller_in(0), Load, Clock, Q(0) ) ; END Structure ;,14,Component 與Port Map:乘法器架構,15,Component 與Port Map:乘法器架構(續),architecture a of mult is component adder port (cin: in STD_LOGIC; a,b: in STD_LOGIC_VECTOR (2 downto 0); x

16、: out STD_LOGIC_VECTOR (2 downto 0); cout: out STD_LOGIC ); end component; signal pp0, pp1, pp2, spp0: STD_LOGIC_VECTOR (2 downto 0); signal isum: STD_LOGIC_VECTOR (3 downto 0); signal zero: STD_LOGIC; begin zero = 0; pp0 = a when b(0) = 1 else 000; pp1 = a when b(1) = 1 else 000; pp2 = a when b(2)

17、= 1 else 000; spp0 = 0 ,Hierarchical design: Generic的使用,16,Generic提供VHDL語言中可以訂定元件參數模型的能力，下面我們舉幾個N位元加法器、N位元暫存器或計數器等的電路設計作為實例。在程式中我們利用Generic指令來指定N的大小，之後可以很彈性的透過N值的更改而馬上將該電路變成N位元的架構。,Delay Bit Width,Generic的使用Example:N位元三態閘,17,LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY tri_n IS GENERIC ( N :

18、INTEGER := 8 ) ; PORT (X : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; E : IN STD_LOGIC ; F : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END tri_n ; ARCHITECTURE Behavior OF tri_n IS BEGIN F Z) WHEN E = 0 ELSE X ; END Behavior ;,Generic的使用Example:N位元加法器設計,18,architecture a of adderN is component adder port ( a

19、: in std_logic; b : in std_logic; cin : in std_logic; sum : out std_logic; cout : out std_logic); end component; signal carry : std_logic_vector(0 to N); begin carry(0) a(I), b = b(I), cin = carry(I - 1), sum = sum(I), cout = carry(I); end generate; end a;,library IEEE; use IEEE.std_logic_1164.all;

20、entity adderN is generic(N : integer := 8); port ( a,b : in std_logic_vector(N downto 1); cin : in std_logic; sum : out std_logic_vector(N downto 1); cout : out std_logic); end adderN;,Generic的使用Example:N位元暫存器,19,library ieee; use ieee.std_logic_1164.all; entity regn is generic (size: integer := 4);

21、 port (EN, clk : in std_logic; D_data : in std_logic_vector (size - 1 downto 0); Q_data : out std_logic_vector (size - 1 downto 0); end regn;,architecture behavioral of regn is begin process(clk) begin if clkevent and clk=1 then if EN = 1 then Q_data = D_data; end if; end if; end process; end behavi

22、oral;,Generic的使用Example:N位元移位暫存器,20,ARCHITECTURE Behavior OF shiftN IS BEGIN PROCESS ( Rst, Clock ) BEGIN IF Rst= 1 THEN Q 0) ; ELSIF ClockEVENT AND Clock = 1 THEN G1: FOR i IN N DOWNTO 2 LOOP Q(i) = Q(i-1) ; END LOOP ; Q(1) = serial_in ; END IF ; END PROCESS ; END Behavior ;,LIBRARY ieee ; USE ieee

23、.std_logic_1164.all ; ENTITY shiftN IS GENERIC ( N : INTEGER := 4 ) ; PORT ( Rst, Clock, serial_in : IN STD_LOGIC ; Q : BUFFER STD_LOGIC_VECTOR(1 TO N) ) ; END shiftN ;,Generic的使用Example,21,architecture a of DFF_WREN is signal F, D_OUT : std_logic_vector(N-1 downto 0); begin process (en, D, D_OUT) b

24、egin case en is when 1 = F F = D_OUT; end case; end process; process (clk) begin if clkevent and clk = 1 then D_OUT = F; end if; end process; Q = D_OUT; end a;,library IEEE; use IEEE.std_logic_1164.all; entity DFF_WREN is generic(N:integer:=8); port( D : in std_logic_vector(N-1 downto 0); Q : out st

25、d_logic_vector(N-1 downto 0); en : in std_logic; clk : in std_logic); end DFF_WREN;,Generic的使用Example :Q=A0+A1+A2+AN,22,entity D_ACC is generic(N:integer:=8); port(A :in std_logic_vector(N-1 downto 0); reset,clk : in std_logic; OE : in std_logic; Q:out std_logic_vector(2*N-1 downto 0); end D_ACC;,ar

26、chitecture a of D_ACC is signal B,X:std_logic_vector(2*N-1 downto 0); begin process (A,B) begin X Q Z); when others = Q 0); else B = X; end if; end if; end process; end a;,Hierarchical design: For-Generate敘述,23,VHDL程式提供了For-Generate敘述來描述一些具有重覆性特性的電路，它雖然以迴圈的型式來撰寫，但本身卻是屬於並行敘述指令之一，不可放在Process指令敘述中使用。,其

27、格式如下：,例如：,For-Generate敘述:以Generate 敘述設計一四位元加法器,24,ARCHITECTURE a OF full_add4 IS component FULL_ADD port(SA,SB,SCin:in bit; Scout,SUM :out bit); end component; signal CARRY:bit_vector(4 downto 0); BEGIN CARRY(0)=cin; G1:for I in 3 downto 0 generate FA:FULL_ADD port map (CARRY(I),A(I),B(I),CARRY(I+1)

28、,SUM(I); end generate G1; cout=CARRY(4); END a;,For-Generate敘述十六對一的多工器電路,25,ARCHITECTURE Structure OF mux16to1 IS component mux4to1 PORT (D0, D1, D2, D3: IN STD_LOGIC ; s: IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; Y: OUT STD_LOGIC ) ; END component ; SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ; BEGIN G1: FOR I IN

29、0 TO 3 GENERATE Muxes: mux4to1 PORT MAP (D(4*i), D(4*i+1), D(4*i+2),D(4*i+3), s(1 DOWNTO 0), m(i) ) ; END GENERATE ;,For-Generate敘述Example:移位暫存器,26,ARCHITECTURE a OF counter4 IS component dff_v PORT(D,CLK: INSTD_LOGIC; Q: OUTSTD_LOGIC); end component; BEGIN GI:for I in 0 to 3 generate GI0: if I=0 generate cell:dff_v port map (input,clock,Q(I); end generate GI0; GI1_3: if I0 generate cell: