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本科生毕业论文(设计)第 1 页 共 9 页英文原文英文原文英文原文英文原文原文出处:原文出处:原文出处:原文出处:DOUGLASLP.VHDL:programming by exampleMNew York:McGrawHillProfessional2002FOREWORDFOREWORDFOREWORDFOREWORDVHDL has beenatthe heart ofelectronic design productivity since initialratification bythe IEEE in 1987. For almost15 years the electronic designautomation industry has expanded the useofVHDL from initial concept ofdesigndocumentation, to design implementation and func tional verification.Itcanbesaid that VHDL fueled modern synthesis technology and enabled the developmentofASIC semiconductor companies. This bookhas served as the authoritativesourceof practicalinformation on the use ofVHDL for users ofthe languagearound the world.The use ofVHDL has evolved and its importanceincreased as semi conductordevices dimensions have shrunk. Not more than 10 years agoitwas common tomix designs described with schematics and VHDL. But as design complexity grew,the industry abandoned schematics in favor ofthe hardware description languageonly. Thesuccessive revisions ofthis book have always kept pace with theindustrysevolving use ofVHDL.The fact that VHDLisadaptableis atribute to its architecture. The industryhas seenthe useof VHDLspackage structure to allow design ers, electronicdesign automation companies and the semiconductorindus try to experiment withnew language conceptsto ensure good design tooland data interoperability. Whenthe associated data types found in the IEEE 1164 standard were ratified,itmeantthat design data interoper ability was possible.Allofthis was facilitated byindustry backing inaconsortium of systems,electronic design automation and semiconductorcompanies now known asAccellera.And when the ASIC industry neededastandard way to convey gate-leveldesign data and timing information in VHDL, one ofAccellerasprogenitors本科生毕业论文(设计)第 2 页 共 9 页(VHDL International) sponsored the IEEE VHDL team to buildacompanionstandard. TheIEEE 1076.4 VITAL (VHDL Initiative Towards ASIC Libraries)was created and ratified as offers designersasingle language flow from concept togate-level signoff.Inthe late90s, the Verilog HDL and VHDL industry standards teamscollaborated onthe useofacommon timing data suchas IEEE 1497 SDF, setregister transferlevel (RTL) standards and more to improvedesign methodologiesand the external connections provided to the hardware description languages.But from the beginning, the leadership ofthe VHDL community has assuredopen and internationally accredited standards forthe electronic design engineeringcommunity. The legacy of this teamswork continues to benefit the designcommunity todayas thebenchmark bywhich onemeasures openness.The design community continues to seebenefits as the electronic designautomation community continues to find new algorithms to work from VHDLdesign descriptions and related standards to again push designer productivity.And,asanew generation of designers ofprogrammable logic devices move to the useofhardware description languages as the basis oftheir design methodology, therewillbesubstantial growth in the number ofVHDL users.This new generation of electronic designers, along with the current designersofcomplex systems and ASICs,willfind this book invaluable . Updatedwithcurrent ue ofthe standard,all willbenefit from the years ofuse that have made theVHDL languagethe underpinning ofsuccessful electronic design.IntroductionIntroductionIntroductionIntroductiontotototoVHDLVHDLVHDLVHDLThe VHSIC Hardware Description Languageisan industry standard languageused to describe hardware from the abstract to the concrete level. VHDL resultedfrom work done in the70s and early80s bythe U.S.Department ofDefense. Itsroots are in the ADA language, aswillbeseen bythe overall structure ofVHDL aswell as other VHDL statements.VHDL usage has risen rapidly since its inception andisused byliterally tensofthousands ofengineers around the globe to create sophisticated electronicproducts. This chapter will start the process ofeasing the reader into the本科生毕业论文(设计)第 3 页 共 9 页complexities ofVHDL. VHDLis apowerful language with numerous languageconstructs that are capable ofdescribing very complex behavior. Learningallthefeatures ofVHDLisnotasimple task. Complex featureswillbe introduced inasimple form and then more complex usagewillbedescribed.In 1986, VHDL was proposed as an IEEE standard.Itwent throughanumberofrevisions and changes untilitwas adopted as the IEEE 1076 standard inDecember 1987. The IEEE 1076-1987 standard VHDListhe VHDL used in thisbook.(AppendixDcontainsabrief description ofVHDL 1076-1993.)Alltheexamples have been described in IEEE 1076 VHDL, and compiled and simulatedwith the VHDL simulation environment from Model Technology Inc.VHDLVHDLVHDLVHDLTermsTermsTermsTermsBefore we go any further, letsdefine some of the terms that we usethroughout the book. Theseare the basic VHDL building blocks that are used inalmostevery description, along with some terms that are redefined in VHDL tomean something different tothe average designer.Entity.Alldesigns are expressed in terms of entities. An entityisthe mostbasic building block inadesign. The uppermostlevel of the designisthe top-levelentity.Ifthe designishierarchical, then the top-level descriptionwillhavelowerleveldescriptionscontained in it. These lower-leveldescriptionswillbelowerlevelmentities contained in the top-level entity description.Architecture.Allentities that canbe simulated have an architecturedescription. The architecture describes the behavior ofthe entity.Asingle entitycan have multiple architectures. One architecture might bebehavioralwhileanother might beastructural description ofthe design.Configuration.Aconfiguration statementisused to bindacomponentinstance to an entity-architecture pair. A configuration canbeconsidered likeaparts list foradesign.Itdescribes which behavior to useforeach entity, much likeaparts list describes which partto usefor eachpart in the design.Package.A packageis acollection ofcommonly used data types andsubprograms used inadesign. Think ofapackage asatoolboxthat containstools used to build designs.Driver.Thisis asource onasignal.If asignalisdriven bytwo sources, then本科生毕业论文(设计)第 4 页 共 9 页when both sources are active, the signalwillhave two drivers.Bus.Theterm“bus”usually brings to mindagroup ofsignals oraparticularmethod ofcommunication used in the design ofhardware. In VHDL,abusis aspecialkind of signal that may have its drivers turned off.Attribute.An attributeisdatathat are attached to VHDL objects or predefineddata about VHDL objects. Examples are the current drive capability ofabuffer orthe maximum operating temperature ofthe device.Generic.A genericisVHDLsterm foraparameter that passes information toan entity. For instance,ifan entityis agate level modelwitharise andafalldelay,values for the rise andfalldelays could bepassed into the entity with generics.Process.Aprocessisthe basic unit ofexecution in VHDL.Alloperations thatare performed inasimulation ofaVHDL description are broken into single ormultiple processes.DescribingDescribingDescribingDescribingHardwareHardwareHardwareHardwareininininVHDLVHDLVHDLVHDLVHDL Descriptions consistof primary design units and secondary designunits. Theprimary design units are the Entity and the Package. The secondarydesign units are the Architecture and the Package Body. Secondarydesign units arealways related toaprimary design unit. Libraries are collections ofprimary andsecondary design units.Atypicaldesign usually contains oneor more libraries ofdesign units.EntityEntityEntityEntityAVHDL entity specifies the name ofthe entity, the ports ofthe entity, andentityrelated information.Alldesigns are created using oneor more entities. Letstakealookat asimple entity example:ENTITY mux ISPORT(a, b, c, d:IN BIT;s0, s1:IN BIT; x,:OUT BIT);END mux;The keyword ENTITY signifies that thisisthe start ofan entity statement. Inthe descriptions shown throughout the book, keywords ofthe language and typesprovided with the STANDARD package are shown in ALL CAPITAL letters. Forinstance, in the preceding example, the keywords are ENTITY, IS, PORT, IN,本科生毕业论文(设计)第 5 页 共 9 页INOUT, and so on. The standard type providedisBIT. Names ofuser-createdobjects suchas mux, in the example above,willbe shown in lower case.The name ofthe entityismux. Theentity has seven ports in the PORTclause.Six ports are ofmodeINand oneportisofmodeOUT. The four datainput ports(a,b, c, d)are oftype BIT. The two multiplexer select inputs, s0 and s1, are also oftype BIT. The outputportisoftype BIT. Theentity describes the interface to theoutside world.Itspecifies the number ofports, the direction ofthe ports, and thetype ofthe ports.Alot more information can beput into the entity thanisshownhere, but this gives usafoundation upon which we can build more complexexamples.ArchitecturesArchitecturesArchitecturesArchitecturesThe entity describes the interface to the VHDL model. The architecturedescribes the underlying functionality ofthe entity and contains the statements thatmodelthe behavior ofthe entity. An architectureisalways related to an entity anddescribes the behavior ofthat entity. An architecture for the counter devicedescribed earlier would look like this:ARCHITECTURE dataflow OFmux ISSIGNAL select:INTEGER;BEGINselect = 0 WHEN s0 =0AND s1 =0ELSE1 WHEN s0 =1AND s1=0ELSE2 WHENs0 =0AND s1 =1ELSE3;x = a AFTER 0.5 NSWHEN select = 0 ELSEb AFTER 0.5 NSWHENselect = 1 ELSEc AFTER 0.5 NS WHEN select = 2 ELSEd AFTER 0.5 NS;END dataflow;The keywordARCHITECTUREsignifies that this statement describes anarchitecture foran entity. The architecture nameisdataflow. Theentitythe architectureisdescribingiscalled mux.The reasonfor the connection between the architecture and the entityisthatan entity can have multiple architectures describing the behavior ofthe entity. Forinstance, one architecture could beabehavioral description, and another could beastructuraldescription.The textualarea between the keyword ARCHITECTURE and the keywordBEGINiswhere local signals and components are declared for later use.Inthis本科生毕业论文(设计)第 6 页 共 9 页example signal selectisdeclared to bealocal signal.The statement area ofthe architecture starts with the keyword BEGIN.Allstatements between the BEGINand the ENDnetlist statement are calledconcurrent statements, becauseallthe statements execute concurrently.DefaultDefaultDefaultDefaultConfigurationsConfigurationsConfigurationsConfigurationsThe simplest form ofexplicit configurationisthe default configuration. Thisconfiguration can beused formodels that donot contain any blocks orcomponentsto configure. The default configuration specifies the configuration name, the entitybeing configured, and the architecture to be usedfor the entity. Followingisanexample oftwo default configurations shown byconfigurations big_count andsmall_count:LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;ENTITY counter ISPORT(load, clear, clk:IN std_logic;PORT(data_in:IN INTEGER;PORT(data_out:OUT INTEGER);END counter;ARCHITECTURE count_255 OF counter ISBEGINPROCESS(clk)VARIABLE count:INTEGER := 0;BEGINIF clear =1THENcount := 0;ELSIF load =1THENcount := data_in;ELSEIF (clkEVENT) AND (clk =1)AND本科生毕业论文(设计)第 7 页 共 9 页(clkLAST_VALUE =0)THENIF (count = 255) THENcount := 0;ELSEcount := count + 1;END IF;END IF;END IF;data_out = count;END PROCESS;END count_255;ARCHITECTURE count_64k OF counter ISBEGINPROCESS(clk)VARIABLE count:INTEGER := 0;BEGINIF clear =1THENcount := 0;ELSIF load =1THENcount := data_in;ELSEIF (clkEVENT) AND (clk =1)AND(clkLAST_VALUE =0)THENIF (count = 65535) THENcount := 0;ELSEcount := count + 1;END IF;END IF;END IF;data_out = count;本科生毕业论文(设计)第 8 页 共 9 页END PROCESS;END count_64k;CONFIGURATION small_count OFcounter ISFOR count_255END FOR;END small_count;CONFIGURATION big_count OFcounter ISFOR count_64kEND FOR;END big_count;This example shows how two different architectures foracounter entity canbeconfigured using two default configurations. The entity for the counter does notspecify any bit width forthe datato beloaded into the counter ordata from thecounter. The data type forthe input and outputdataisINTEGER.Withadata typeofinteger, multiple types of counters can besupported up to the integerrepresentation limit of the host computer forthe VHDL simulator.Thetwo architectures ofentity counter specify two different-sized countersthat canbeused for the entity. The first architecture, count_255count_255count_255count_255, specifies an 8-bitcounter. The secondarchitecture, count_64kcount_64kcount_64kcount_64k, specifiesa16-bit counter. Thearchitectures specifyasynchronous counter withasynchronous loadloadloadloadand clearclearclearclear.Alloperations forthe device occur with respect to the clock.Each ofthe two configurations for the entity specifiesadifferent architectureforthe counter entity. Letsexamine the firstconfiguration in more detail. Theconfiguration de
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