Ch5_Altera_JTAG(4)

1、PLD,JTAG interface,Reference,AN 39: JTAG Boundary-Scan Testing in Altera Devices Altera Co. AN 88: Using the Jam Language for ISP & ICR via an Embedded Processor Altera Co. IEEE Standard Test Access Port and Boundary-Scan Architecture IEEE Std 1149.1-2001 (Revision of IEEE Std 1149.1-1990),What is J

2、TAG?,JTAG Joint Test Action Group BST A standard Boundary-Scan Testing interface,Why JTAG?,A uniform interface for device testing Daisy chain structure to testing multiple IC from one testing interface On-line testing and programming Provides extra function such as CPU debugging and board bus contro

3、l,History of JTAG,1985 Joint European Test Action Group(JETAG) was formed in Europe 1986 The group expanded to include members from both Europe and North America and was renamed the Joint Test Action Group (JTAG). 1988 JTAG Version 2.0was offered to the IEEE Testability Bus Standards Committee (P114

4、9) 1993 IEEE Std 1149.1a-1993,Boundary-scan Testing,Feature of BST,Offers the capability to efficiently test components on PCBs with tight lead spacing. Test pin connections without using physical test probes and capture functional data while a device is operating normally. Force signals onto pins,

5、or capture data from pin or core logic signals. Forced test data is serially shifted into the boundary-scan cells. Captured data is serially shifted out and externally compared to expected results.,BST Pins for Altera MAX7000A,Description of BST Pins,Functional Model IEEE Std. 1149.1 Circuitry,Regis

6、ters of BST,Boundary-scan Register which is a shift register composed of all the boundary-scan cells of the device. Bypass Register which is a 1-bit-long data register used to provide a minimum-length serial path between TDI and TDO Instruction Register which is used to determine the action to be pe

7、rformed and the data register to be accesse,Test clock input pin (TCK),Many parts of the test logic perform operations in response to the rising or falling edge of TCK Be driven by a free-running clock with a nominal 50% duty cycle May vary significantly in frequency from one component to the anothe

8、r,Test mode select input (TMS),The signal received at TMS is decoded by the TAP controller to control test operations. TMS shall be sampled by the test logic on the rising edge of TCK. Change the signal driven to the TMS inputs of connected components on the falling edge of TCK. Design TMS pin caref

9、ully to avoid entering test mode by a voltage on un-driven TMS pin. A pull-up resistor is recommended,Test data input (TDI),Serial test instructions and data are received by the test logic at TDI. Signal presented at TDI shall be sampled into the test logic on the rising edge of TCK. The bus master

10、will change the signal driven to the TDI input on the falling edge of TCK. The design of the circuitry should ensure that an un-driven input produces a logic 1. (Pull-up resistor),Test data output (TDO),TDO is the serial output for test instructions and data from the test logic Changes in the state

11、of the signal driven through TDO occurs on the falling edge of TCK. External logic sample TDO on the rising edge of TCK.,Test reset input (TRST),Optional Provides for asynchronous initialization of the TAP controller TMS should be held at 1 while the signal applied at TRST changes from 0 to 1. Undri

12、ven input produces a logical response identical to the application of a logic 1. (Pull-up resistor),Pull-up Registers For TAP Controller,Reset of JTAG,Test Access Port,TAP controller is controlled by 5 pins TMS TRST TCK,TAP FSM,Boundary-scan Register (1),Boundary-scan Register in Alter Devices (1),B

13、oundary-scan Register in Alter Devices (2),Boundary-scan Register Cell of Altera MAX7000 (IO),Boundary-scan Register Cell of Altera MAX7000 (IN),TAP FSM,Timing of Actions in a Controller State,Waveform for Instruction Scan,Waveform for Data Scan,TEST_LOGIC/RESET State,The BST circuitry is disabled T

14、he device is in normal operation The instruction register is initialized. Initial instruction is IDCODE or BYPASS (if IDCODE is not supported). Enter TEST_LOGIC/RESET Mode device power-up Can be forced to the TEST_LOGIC/RESET state by holding TMS high for five TCK clock cycles holding the TRST pin l

15、ow (if the optional TRST pin is supported.),How to reach SHIFT_IR state?,SHIFT_IR state,Shift in the instruction code into “instruction register” TDO pin It is activated at the first falling edge of TCK after entering shift states and is tri-stated at the first falling edge of TCK after leaving shif

16、t states. When shift data in SHIFT_IR state, the initial state of the instruction register is shifted out on the falling edge of TCK while new instruction is shifted in from TDI pin TDI pin Instruction code is entered by shifting data on the TDI pin on the rising edge of TCK The last bit of the opco

17、de must be clocked at the same time that the next state, EXIT1_IR, is activated The circuits exit “SHIFT_IR” state by entering EXIT1_IR state,EXIT1_IR State,EXIT1_IR is entered at the end of SHIFT_IR operation, by clocking a logic high on TMS Can put the controller to enter the Update-IR state (TMS

18、= H for next rising edge of TCK) In EXIT1_IR state TDO becomes tri-stated again After an instruction code is entered correctly, the TAP controller advances to perform the serial shifting of test data in one of three modesSAMPLE/PRELOAD, EXTEST, or BYPASSthat are described below.,PAUSE_IR State,Allow

19、s shifting of the instruction register to be halted temporarily (and can continue SHIFT_IR again later),EXIT2_IR State,A temporary controller state A last chance to ask JTAG user, whether to go on updating instruction register or continue shifting instruction If TMS = H and a rising edge is applied

20、to TCK while in this state, the TAP controller enters the Update-IR controller If TMS is held low and a rising edge is applied to TCK, the controller enters the Shift-IR state,UPDATE-IR State,The instruction shifted into the instruction register is latched onto the parallel output from the shift-reg

21、ister path on the falling edge of TCK in this controller state. Once the new instruction has been latched, it becomes the current instruction.,Recommended Instruction by IEEE,Instruction Code for Altera PLDs,SAMPLE/PRELOAD Instruction Mode,Allows user to take a snapshot of device data without interr

22、upting normal device operation. Phases Capture Phase Shift & Update Phases,Capture Phase,Shift & Update Phases,SAMPLE/PRELOAD Shift Data Register Waveforms,EXTEST Instruction Mode,Is used primarily to check external pin connections between devices. Unlike the SAMPLE/PRELOAD mode, EXTEST allows test

23、data to be forced onto the pin signals. By forcing known logic high and low levels on output pins, opens and shorts can be detected at pins of any device in the scan chain. Phase Capture Phase Shift & Update phase,Capture Phase,Shift & Update Phases,Waveform,SAMPLE/PRELOAD Mode vs. EXTEST Mode,SAMPL

24、E/PRELOAD Mode EXTEST Mode,BYPASS Instruction Mode (1),BYPASS Instruction Mode (2),The BYPASS instruction mode is activated with an instruction code made up of only ones. Through a device once the TAP controller is in the SHIFT_DR state. In this state, data signals are clocked into the bypass regist

25、er from TDI on the rising edge of TCK and out of TDO on the falling edge of the same clock pulse.,Waveform,IDCODE Instruction Mode,The IDCODE instruction mode is used to identify the devices in an IEEE Std. 1149.1 chain. When IDCODE is selected, the device identification register is loaded with the

26、32-bit vendor-defined identification code and connected between the TDI and TDO ports.,32-bit ID of Altera MAX7000,USERCODE Instruction Mode,The USERCODE instruction mode is used to examine the user electronic signature (UES) within the devices along an IEEE Std. 1149.1 chain. The device identificat

27、ion register is connected between the TDI and TDO ports and the user-defined UES is shifted out through the device ID register. This instruction is required only for programmable components in which the programming cannot be determined through use of the test logic.,Init of TAP,Power on TRST pin No

28、matter what the original state of the controller, it will enter Test-Logic-Reset when TMS is held high for at least five rising edges of TCK.,Boundary-Scan Description Language (BSDL),A subset of VHDL Provides a syntax that allows you to describe the features of an IEEE Std. 1149.1 BST-capable devic

29、e that can be tested.,Scope of BSDL,Components of a BSDL description (1),Components of a BSDL description (2),The entity description Specify component-specific parameters of the test logic. The Standard VHDL Package and Standard VHDL Package Body The Standard VHDL Package shall give a definition of

30、the BSDL subset of VHDL, which is required to allow BSDL descriptions to be read by a VHDL-conformant parser. The Standard VHDL Package Body shall give definitions of commonly used types of boundary-scan register cells. User-specified VHDL packages and VHDL package bodies define boundary-scan regist

31、er cell designs specific to any group of components.,JTAG Timing,JTAG timing for Altera MAX7000,Connection Modes (1),Connection Modes (2),Dead Lock in JTAG,Mother Board & Daughter Board,ISP & ICR Using JTAG,ISP in-system programmability ICR in-circuit reconfigurability,Download Code to Altera CPLD,Byte Blas