mips芯片资料mips32-3

1、MIPS32 Architecture For Programmers Volume III: The MIPS32 Privileged ResourceArchitectureDocument Number: MD00090 Revision 1.90September 1, 2002MIPS Technologies, Inc. 1225 Charleston RoadMountain View, CA 94043-1353Copyright 2001-2002 MIPS Technologies Inc. All rights reserved.Copyright 2001-2002

2、MIPS Technologies, Inc. All rights reserved.Unpublished rights (if any) are reserved under the Copyright Laws of the United States of America.If this document is provided in source format (i.e., in a modifiable form such as in FrameMaker or Microsoft Word format), then its use and distribution is su

3、bject to a written agreement with MIPS Technologies, Inc. (MIPS Technologies). UNDER NO CIRCUMSTANCES MAY A DOCUMENT PROVIDED IN SOURCE FORMAT BE DISTRIBUTED TO A THIRD PARTY WITHOUT THE EXPRESS WRITTEN CONSENT OF MIPS TECHNOLOGIES.This document contains information that is proprietary to MIPS Techn

4、ologies. Any copying, reproducing, modifying, or use of this information (in whole or in part) which is not expressly permitted in writing by MIPS Technologies or acontractually-authorized third party is strictly prohibited. At a minimum, this information is protected under unfair competition and co

5、pyright laws. Violations thereof may result in criminal penalties and fines.MIPS Technologies or any contractually-authorized third party reserves the right to change the information contained in this document to improve function, design or otherwise. MIPS Technologies does not assume any liability

6、arising out of the application or use of this information, or of any error of omission in such information. Any warranties, whether express, statutory, implied or otherwise, including but not limited to the implied warranties of merchantability or fitness for a particular purpose, are excluded. Any

7、license under patent rights or any other intellectual property rights owned by MIPS Technologies or third parties shall be conveyed by MIPS Technologies or any contractually-authorized third party in a separate license agreement between the parties.The information contained in this document shall no

8、t be exported or transferred for the purpose of reexporting in violation of any U.S. or non-U.S. regulation, treaty, Executive Order, law, statute, amendment or supplement thereto.The information contained in this document constitutes one or more of the following: commercial computer software, comme

9、rcial computer software documentation or other commercial items. If the user of this information, or any related documentation of any kind, including related technical data or manuals, is an agency, department, or other entity of the United States government (“Government”), the use, duplication, rep

10、roduction, release, modification, disclosure, or transfer of this information, or any related documentation of any kind, is restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies.

11、The use of this information by the Government is further restricted in accordance with the terms of the license agreement(s) and/or applicable contract terms and conditions covering this information from MIPS Technologies or any contractually-authorized third party.MIPS, R3000, R4000, R5000 and R100

12、00 are among the registered trademarks of MIPS Technologies, Inc. in the United States and certain other countries, and MIPS16, MIPS16e, MIPS32, MIPS64, MIPS-3D, MIPS-based, MIPS I, MIPS II, MIPS III, MIPS IV, MIPS V, MDMX, MIPSsim, MIPSsimCA, MIPSsimIA,QuickMIPS, SmartMIPS, MIPS Technologies logo,

13、4K, 4Kc, 4Km, 4Kp, 4KE, 4KEc, 4KEm, 4KEp, 4KS, 4KSc, M4K, 5K, 5Kc, 5Kf, 20K, 20Kc, 25Kf, R4300, ASMACRO, ATLAS, BusBridge, CoreFPGA, CoreLV, EC, JALGO, MALTA, MGB, PDtrace, SEAD, SEAD-2, SOC-it, The Pipeline, and YAMON are among the trademarks of MIPS Technologies, Inc.All other trademarks referred

14、to herein are the property of their respective owners.Template: B1.06, Build with Conditional Tags: 2B ARCH MIPS32MIPS32 Architecture For Programmers Volume III, Revision 1.90Copyright 2001-2002 MIPS Technologies Inc. All rights reserved.Table of ContentsChapter 1 About This Book11.1Typographical Co

15、nventions11.1.11.1.21.1.3Italic Text1Bold Text1Courier Text11.2UNPREDICTABLE and UNDEFINED21.2.1 UNPREDICTABLE21.2.2 UNDEFINED2Special Symbols in Pseudocode Notation2For More Information41.31.4Chapter 2 The MIPS32 Privileged Resource Architecture72.1 Introduction72.2 The MIPS Coprocessor Model72.2.1

16、 CP0 - The System Coprocessor72.2.2 CP0 Registers7Chapter 3 MIPS32 Operating Modes93.13.23.33.43.5Debug Mode9Kernel Mode9Supervisor Mode9User Mode10Other Modes103.5.1 64-bit Floating Point Operations Enable.103.5.2 64-bit FPR Enable10Chapter 4 Virtual Memory114.1Support in Release 1 and Release 2 of

17、 the Architecture114.1.1 Virtual Memory11Terminology114.24.2.14.2.24.2.3Address Space11Segment and Segment Size11Physical Address Size (PABITS).114.34.44.54.64.74.84.9Virtual Address Spaces12Compliance14Access Control as a Function of Address and Operating Mode14Address Translation and Cache Coheren

18、cy Attributes for the kseg0 and kseg1 Segments15Address Translation for the kuseg Segment when StatusERL = 116Special Behavior for the kseg3 Segment when DebugDM = 116TLB-Based Virtual Address Translation164.9.14.9.24.9.3Address Space Identifiers (ASID)16TLB Organization17Address Translation17Chapte

19、r 5 Interrupts and Exceptions215.1 Interrupts215.1.1 Interrupt Modes225.1.2 Generation of Exception Vector Offsets for Vectored Interrupts295.2 Exceptions305.2.15.2.25.2.3Exception Vector Locations30General Exception Processing32EJTAG Debug Exception34MIPS32 Architecture For Programmers Volume III,

20、Revision 1.90iCopyright 2001-2002 MIPS Technologies Inc. All rights reserved.5.2.45.2.55.2.65.2.75.2.85.2.9Reset Exception34Soft Reset Exception35Non Maskable Interrupt (NMI) Exception36Machine Check Exception37Address Error Exception37TLB Refill Exception385.2.105.2.115.2.125.2.135.2.145.2.155.2.16

21、5.2.175.2.185.2.195.2.205.2.215.2.225.2.23TLB Invalid Exception38TLB Modified Exception39Cache Error Exception39Bus Error Exception40Integer Overflow Exception40Trap Exception41System Call Exception41Breakpoint Exception.41Reserved Instruction Exception41Coprocessor Unusable Exception42Floating Poin

22、t Exception43Coprocessor 2 Exception43Watch Exception43Interrupt Exception44Chapter 6 GPR Shadow Registers456.1 Introduction to Shadow Sets456.2 Support Instructions46Chapter 7 CP0 Hazards477.17.2Introduction47Types of Hazards477.2.1 Execution Hazards477.2.2 Instruction Hazards48Hazard Clearing Inst

23、ructions497.3.1 Instruction Encoding497.3Chapter 8 Coprocessor 0 Registers518.18.28.38.48.58.68.78.88.9Coprocessor 0 Register Summary51Notation54Index Register (CP0 Register 0, Select 0)55Random Register (CP0 Register 1, Select 0)56EntryLo0, EntryLo1 (CP0 Registers 2 and 3, Select 0)57Context Regist

24、er (CP0 Register 4, Select 0)61PageMask Register (CP0 Register 5, Select 0)62PageGrain Register (CP0 Register 5, Select 1)64Wired Register (CP0 Register 6, Select 0)668.108.118.128.138.148.158.168.178.188.198.208.218.22HWREna Register (CP0 Register 7, Select 0)67BadVAddr Register (CP0 Register 8, Se

25、lect 0)68Count Register (CP0 Register 9, Select 0)69Reserved for Implementations (CP0 Register 9, Selects 6 and 7)69EntryHi Register (CP0 Register 10, Select 0)70Compare Register (CP0 Register 11, Select 0)72Reserved for Implementations (CP0 Register 11, Selects 6 and 7)72Status Register (CP Registe

26、r 12, Select 0)73IntCtl Register (CP0 Register 12, Select 1)79SRSCtl Register (CP0 Register 12, Select 2)81SRSMap Register (CP0 Register 12, Select 3)83Cause Register (CP0 Register 13, Select 0)84Exception Program Counter (CP0 Register 14, Select 0)88iiMIPS32 Architecture For Programmers Volume III,

27、 Revision 1.90Copyright 2001-2002 MIPS Technologies Inc. All rights reserved.8.22.1 Special Handling of the EPC Register in Processors That Implement the MIPS16e ASE.88Processor Identification (CP0 Register 15, Select 0)89EBase Register (CP0 Register 15, Select 1)90Configuration Register (CP0 Regist

28、er 16, Select 0)91Configuration Register 1 (CP0 Register 16, Select 1)93Configuration Register 2 (CP0 Register 16, Select 2)97Configuration Register 3 (CP0 Register 16, Select 3)100Reserved for Implementations (CP0 Register 16, Selects 6 and 7)102Load Linked Address (CP0 Register 17, Select 0)103Wat

29、chLo Register (CP0 Register 18)104WatchHi Register (CP0 Register 19)105Reserved for Implementations (CP0 Register 22, all Select values)107Debug Register (CP0 Register 23)108DEPC Register (CP0 Register 24)1098.35.1 Special Handling of the DEPC Register in Processors That Implement the MIPS16e ASE109

30、Performance Counter Register (CP0 Register 25)110ErrCtl Register (CP0 Register 26, Select 0)113CacheErr Register (CP0 Register 27, Select 0)114TagLo Register (CP0 Register 28, Select 0, 2)115DataLo Register (CP0 Register 28, Select 1, 3)116TagHi Register (CP0 Register 29, Select 0, 2)117DataHi Regis

31、ter (CP0 Register 29, Select 1, 3)118ErrorEPC (CP0 Register 30, Select 0)1198.43.1 Special Handling of the ErrorEPC Register in Processors That Implement the MIPS16e ASE1198.238.248.258.268.278.288.298.308.318.328.338.348.358.368.378.388.398.408.418.428.438.44 DESAVE Register (CP0 Register 31)120App

32、endix A Alternative MMU Organizations121A.1 Fixed Mapping MMU121A.1.1A.1.2A.1.3Fixed Address Translation121Cacheability Attributes124Changes to the CP0 Register Interface125A.2 Block Address Translation125A.2.1A.2.2A.2.3BAT Organization125Address Translation126Changes to the CP0 Register Interface12

33、7Appendix B Revision History129MIPS32 Architecture For Programmers Volume III, Revision 1.90iiiCopyright 2001-2002 MIPS Technologies Inc. All rights reserved.List of FiguresFigure 4-1: Virtual Address Space12Figure 4-2: References as a Function of Operating Mode14Figure 4-3: Contents of a TLB Entry1

34、7Figure 5-1: Interrupt Generation for Vectored Interrupt Mode26Figure 5-2: Interrupt Generation for External Interrupt Controller Interrupt Mode28Figure 8-1: Index Register Format55Figure 8-2: Random Register Format56Figure 8-3: EntryLo0, EntryLo1 Register Format in Release 1 of the Architecture57Fi

35、gure 8-4: EntryLo0, EntryLo1 Register Format in Release 2 of the Architecture58Figure 8-5: Context Register Format61Figure 8-6: PageMask Register Format62Figure 8-7: PageGrain Register Format64Figure 8-8: Wired And Random Entries In The TLB66Figure 8-9: Wired Register Format66Figure 8-10: HWREna Reg

36、ister Format67Figure 8-11: BadVAddr Register Format68Figure 8-12: Count Register Format69Figure 8-13: EntryHi Register Format70Figure 8-14: Compare Register Format72Figure 8-15: Status Register Format73Figure 8-16: IntCtl Register Format79Figure 8-17: SRSCtl Register Format81Figure 8-18: SRSMap Regi

37、ster Format83Figure 8-19: Cause Register Format84Figure 8-20: EPC Register Format88Figure 8-21: PRId Register Format89Figure 8-22: EBase Register Format90Figure 8-23: Config Register Format91Figure 8-24: Config1 Register Format93Figure 8-25: Config2 Register Format97Figure 8-26: Config3 Register For

38、mat100Figure 8-27: LLAddr Register Format103Figure 8-28: WatchLo Register Format104Figure 8-29: WatchHi Register Format105Figure 8-30: Performance Counter Control Register Format110Figure 8-31: Performance Counter Counter Register Format112Figure 8-32: ErrorEPC Register Format119Figure 8-33: Memory

39、Mapping when ERL = 0123Figure 8-34: Memory Mapping when ERL = 1124Figure 8-35: Config Register Additions125Figure 8-36: Contents of a BAT Entry126ivMIPS32 Architecture For Programmers Volume III, Revision 1.90Copyright 2001-2002 MIPS Technologies Inc. All rights reserved.List of TablesTable 1-1:Tabl

40、e 4-1:Table 4-2:Table 4-3:Table 4-4:Table 5-1:Table 5-2:Table 5-3:Table 5-4:Table 5-5:Table 5-6:Table 5-7:Table 5-8:Table 6-1:Table 7-1:Table 7-2:Table 7-3:Table 8-1:Table 8-2:Table 8-3:Table 8-4:Table 8-5:Table 8-6:Table 8-7:Table 8-8:Table 8-9:Symbols Used in Instruction Operation Statements2Virtu

41、al Memory Address Spaces13Address Space Access as a Function of Operating Mode15Address Translation and Cache Coherency Attributes for the kseg0 and kseg1 Segments16Physical Address Generation20Interrupt Modes22Request for Interrupt Service in Interrupt Compatibility Mode23Relative Interrupt Priorit

42、y for Vectored Interrupt Mode25Exception Vector Offsets for Vectored Interrupts30Exception Vector Base Addresses31Exception Vector Offsets31Exception Vectors32Value Stored in EPC, ErrorEPC, or DEPC on an Exception33Instructions Supporting Shadow Sets46Execution Hazards47Instruction Hazards48Hazard C

43、learing Instructions49Coprocessor 0 Registers in Numerical Order51Read/Write Bit Field Notation54Index Register Field Descriptions55Random Register Field Descriptions56EntryLo0, EntryLo1 Register Field Descriptions in Release 1 of the Architecture57EntryLo0, EntryLo1 Register Field Descriptions in R

44、elease 2 of the Architecture58EntryLo Field Widths as a Function of PABITS59Cache Coherency Attributes59Context Register Field Descriptions61Table 8-10:Table 8-11:Table 8-12:Table 8-13:Table 8-14:Table 8-15:Table 8-16:Table 8-17:Table 8-18:Table 8-19:Table 8-20:Table 8-21:Table 8-22:Table 8-23:Table

45、 8-24:Table 8-25:Table 8-26:Table 8-27:Table 8-28:Table 8-29:Table 8-30:Table 8-31:Table 8-32:Table 8-33:PageMask Register Field Descriptions62Values for the Mask and MaskX1 Fields of the PageMask Register62PageGrain Register Field Descriptions64Wired Register Field Descriptions66HWREna Register Fie

46、ld Descriptions67BadVAddr Register Field Descriptions68Count Register Field Descriptions69EntryHi Register Field Descriptions70Compare Register Field Descriptions72Status Register Field Descriptions73IntCtl Register Field Descriptions79SRSCtl Register Field Descriptions81Sources for new SRSCtlCSS on

47、 an Exception or Interrupt82SRSMap Register Field Descriptions83Cause Register Field Descriptions84Cause Register ExcCode Field87EPC Register Field Descriptions88PRId Register Field Descriptions89EBase Register Field Descriptions90Config Register Field Descriptions91Config1 Register Field Descriptio

48、ns93Config2 Register Field Descriptions97Config3 Register Field Descriptions100LLAddr Register Field Descriptions103MIPS32 Architecture For Programmers Volume III, Revision 1.90vCopyright 2001-2002 MIPS Technologies Inc. All rights reserved.Table 8-34:Table 8-35:Table 8-36:Table 8-37:Table 8-38:Tabl

49、e 8-39:Table 8-40:Table 8-41:Table 8-42:WatchLo Register Field Descriptions104WatchHi Register Field Descriptions105Example Performance Counter Usage of the PerfCnt CP0 Register110Performance Counter Control Register Field Descriptions111Performance Counter Counter Register Field Descriptions112Erro

50、rEPC Register Field Descriptions119Physical Address Generation from Virtual Addresses121Config Register Field Descriptions125BAT Entry Assignments126viMIPS32 Architecture For Programmers Volume III, Revision 1.90Copyright 2001-2002 MIPS Technologies Inc. All rights reserved.Chapter 1About This BookT

51、he MIPS32 Architecture For Programmers Volume III comes as a multi-volume set.Volume I describes conventions used throughout the document set, and provides an introduction to the MIPS32 ArchitectureVolume II provides detailed descriptions of each instruction in the MIPS32 instruction setVolume III d

52、escribes the MIPS32 Privileged Resource Architecture which defines and governs the behavior of the privileged resources included in a MIPS32 processor implementationVolume IV-a describes the MIPS16e Application-Specific Extension to the MIPS32 ArchitectureVolume IV-b describes the MDMX Application-S

53、pecific Extension to the MIPS32 Architecture and is not applicable to the MIPS32 document setVolume IV-c describes the MIPS-3D Application-Specific Extension to the MIPS64 Architecture and is not applicable to the MIPS32 document setVolume IV-d describes the SmartMIPSApplication-Specific Extension t

54、o the MIPS32 Architecture1.1 Typographical ConventionsThis section describes the use of italic, bold and courier fonts in this book.1.1.1 Italic Textis used for emphasisis used for bits, fields, registers, that are important from a software perspective (for instance, address bits used by software, a

55、nd programmable fields and registers), and various floating point instruction formats, such as S, D, and PSis used for the memory access types, such as cached and uncached1.1.2 Bold Textrepresents a term that is being definedis used for bits and fields that are important from a hardware perspective (for instance, register bits, which are not programmable but accessible only to hardware)is used for ranges of numbers; the range is indicated by an ellipsis. For instance, 5.1 indicates numbers 5 through 1 is used to emphasize UNPREDICTABLE and UNDE