74系列芯片总汇74ls161a_W

1、54LS161A/DM54LS161A/DM74LS161A, 54LS163A/DM54LS163A/DM74LS163A Synchronous4-Bit Binary CountersMay 199254LS161A/DM54LS161A/DM74LS161A,54LS163A/DM54LS163A/DM74LS163ASynchronous 4-Bit Binary CountersGeneral DescriptionThese synchronous, presettable counters feature an inter- nal carry look-ahead for a

2、pplication in high-speed counting designs. The LS161A and LS163A are 4-bit binary counters. The carry output is decoded by means of a NOR gate, thus preventing spikes during the normal counting mode of oper- ation. Synchronous operation is provided by having all flip- flops clocked simultaneously so

3、 that the outputs change co- incident with each other when so instructed by the count- enable inputs and internal gating. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four fli

4、p-flops on the rising (positive-going) edge of the clock input waveform.These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setu

5、p data after the next clock pulse, regardless of the levels of the enable input. The clear function for the LS161A is asynchronous; and a low level at the clear input sets all four of the flip-flop outputs low, regardless of the levels of clock, load, or en- able inputs. The clear function for the L

6、S163A is synchro- nous; and a low level at the clear inputs sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear al- lows the count length to be modified easily, as decoding the maximum count desired can be accom

7、plished with one ex- ternal NAND gate. The gate output is connected to the clear input to synchronously clear the counter to all low outputs.The carry look-ahead circuitry provides for cascading coun- ters for n-bit synchronous applications without additionalgating. Instrumental in accomplishing thi

8、s function are two count-enable inputs and a ripple carry output.Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-lev- el output pulse with a duration approximately equal t

9、o thehigh-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascad- ed stages. High-to-low level transitions at the enable P or T inputs may occur, regardless of the logic level of the clock.These counters feature a fully independent clock c

10、ircuit. Changes made to control inputs (enable P or T or load) that will modify the operating mode have no effect until clocking occurs. The function of the counter (whether enabled, dis- abled, loading, or counting) will be dictated solely by the conditions meeting the stable set-up and hold times.

11、FeaturesY Synchronously programmableY Internal look-ahead for fast countingY Carry output for n-bit cascadingY Synchronous countingY Load control lineY Diode-clamped inputsY Typical propagation time, clock to Q output 14 nsY Typical clock frequency 32 MHzY Typical power dissipation 93 mWY Alternate

12、Military/Aerospace device (54LS161, 54LS163) is available. Contact a National Semiconduc- tor Sales Office/Distributor for specificaitons.Connection DiagramDual-In-Line PackageOrder Numbers 54LS161ADMQB, 54LS161AFMQB, 54LS161ALMQB, 54LS163ADMQB, 54LS163AFMQB,54LS163ALMQB, DM54LS161AJ, DM54LS161AW, D

13、M54LS163AJ, DM54LS163AW, DM74LS161AM, DM74LS161AN, DM74LS163AM or DM74LS163ANSee NS Package Number E20A, J16A, M16A, N16E or W16ATL/F/6397 1C1995 National Semiconductor CorporationTL/F/6397RRD-B30M105/Printed in U. S. A.Absolute Maximum Ratings (Note)If Military/Aerospace specified devices are requi

14、red,Note: The Absolute Maximum Ratings are those values please contact the National Semiconductor Salesbeyond which the safety of the device cannot be guaran- Office/Distributors for availability and specifications.teed. The device should not be operated at these limits. The Supply Voltage7Vparametr

15、ic values defined in the Electrical CharacteristicsInput Voltage7Vtable are not guaranteed at the absolute maximum ratings.The Recommended Operating Conditions table will defineOperating Free Air Temperature Rangethe conditions for actual device operation.DM54LS and 54LSb55?C to a125?C DM74LS0?C to

16、a70?CStorage Temperature Rangeb65?C to a150?CRecommended Operating ConditionsSymbolParameterDM54LS161ADM74LS161AUnitsMinNomMaxMinNomMaxVCCSupply Voltage4.555.54.7555.25VVIHHigh Level Input Voltage22VVILLow Level Input Voltage0.70.8VIOHHigh Level Output Currentb0.4b0.4mAIOLLow Level Output Current48m

17、AfCLKClock Frequency (Note 1)025025MHzClock Frequency (Note 2)020020MHztWPulse Width (Note 1)Clock206206nsClear209209Pulse Width (Note 2)Clock2525nsClear2525tSUSetup Time (Note 1)Data208208nsEnable P25172517Load25152515Setup Time (Note 2)Data2020nsEnable P3030Load3030tHHold Time (Note 1)Data0b30b3ns

18、Others0b30b3Hold Time (Note 2)Data55nsOthers55tRELClear Release Time (Note 1)2020nsClear Release Time (Note 2)2525nsTAFree Air Operating Temperatureb55125070?CNote 1: CL e 15 pF, RL e 2 kX, TA e 25?C and VCC e 5.5V.Note 2: CL e 50 pF, RL e 2 kX, TA e 25?C and VCC e 5.5V.11LS161 Electrical Characteri

19、sticsover recommended operating free air temperature range (unless otherwise noted)SymbolParameterConditionsMinTyp (Note 1)MaxUnitsVIInput Clamp VoltageVCC e Min, II e b18 mAb1.5VVOHHigh Level Output VoltageVCC e Min, IOH e Max VIL e Max, VIH e MinDM542.53.4VDM742.73.4VOLLow Level Output VoltageVCC

20、e Min, IOL e Max VIL e Max, VIH e MinDM540.250.4VDM740.350.5IOL e 4 mA, VCC e MinDM740.250.4IIInput Current Max Input VoltageVCC e Max VI e 7VEnable T0.2mAClock0.2Load0.2Others0.1IIHHigh Level Input CurrentVCC e Max VI e 2.7VEnable T40mAClock40Load40Others20IILLow Level Input CurrentVCC e Max VI e 0

21、.4VEnable Tb0.8mAClockb0.8Loadb0.8Othersb0.4IOSShort Circuit Output CurrentVCC e Max (Note 2)DM54b20b100mADM74b20b100ICCHSupply Current with Outputs HighVCC e Max (Note 3)1831mAICCLSupply Current with Outputs LowVCC e Max (Note 4)1932mANote 1: All typicals are at VCC e 5V, TA e 25?C.Note 2: Not more

22、 than one output should be shorted at a time, and the duration should not exceed one second.Note 3: ICCH is measured with the load high, then again with the load low, with all other inputs high and all outputs open.Note 4: ICCL is measured with the clock input high, then again with the clock input l

23、ow, with all other inputs low and all outputs open.LS161 Switching Characteristicsat VCC e 5V and TA e 25?C (See Section 1 for Test Waveforms and Output Load)SymbolParameterFrom (Input) To (Output)RL e 2 kXUnitsCL e 15 pFCL e 50 pFMinMaxMinMaxfMAXMaximum Clock Frequency2520MHztPLHPropagation Delay T

24、ime Low to High Level OutputClock to Ripple Carry2530nstPHLPropagation Delay Time High to Low Level OutputClock to Ripple Carry3038nstPLHPropagation Delay Time Low to High Level OutputClock to Any Q (Load High)2227nstPHLPropagation Delay Time High to Low Level OutputClock to Any Q (Load High)2738nsL

25、S161 Switching Characteristicsat VCC e 5V and TA e 25?C (See Section 1 for Test Waveforms and Output Load) (Continued)SymbolParameterFrom (Input) To (Output)RL e 2 kXUnitsCL e 15 pFCL e 50 pFMinMaxMinMaxtPLHPropagation Delay Time Low to High Level OutputClock to Any Q (Load Low)2430nstPHLPropagation

26、 Delay Time High to Low Level OutputClock to Any Q (Load Low)2738nstPLHPropagation Delay Time Low to High Level OutputEnable T to Ripple Carry1427nstPHLPropagation Delay Time High to Low Level OutputEnable T to Ripple Carry1527nstPHLPropagation Delay Time High to Low Level OutputClear to Any Q2845ns

27、Recommended Operating ConditionsSymbolParameterDM54LS163ADM74LS163AUnitsMinNomMaxMinNomMaxVCCSupply Voltage4.555.54.7555.25VVIHHigh Level Input Voltage22VVILLow Level Input Voltage0.70.8VIOHHigh Level Output Currentb0.4b0.4mAIOLLow Level Output Current48mAfCLKClock Frequency (Note 1)025025MHzClock F

28、requency (Note 2)020020MHztWPulse Width (Note 1)Clock206206nsClear209209Pulse Width (Note 2)Clock2525nsClear2525tSUSetup Time (Note 1)Data208208nsEnable P25172517Load25152515Setup Time (Note 2)Data2020nsEnable P3030Load3030tHHold Time (Note 1)Data0b30b3nsOthers0b30b3Hold Time (Note 2)Data55nsOthers5

29、5tRELClear Release Time (Note 1)2020nsClear Release Time (Note 2)2525nsTAFree Air Operating Temperatureb55125070?CNote 1: CL e 15 pF, RL e 2 kX, TA e 25?C and VCC e 5V.Note 2: CL e 50 pF, RL e 2 kX, TA e 25?C and VCC e 5V.LS163 Electrical Characteristicsover recommended operating free air temperatur

30、e range (unless otherwise noted)SymbolParameterConditionsMinTyp (Note 1)MaxUnitsVIInput Clamp VoltageVCC e Min, II e b18 mAb1.5VVOHHigh Level Output VoltageVCC e Min, IOH e Max VIL e Max, VIH e MinDM542.53.4VDM742.73.4VOLLow Level Output VoltageVCC e Min, IOL e Max VIL e Max, VIH e MinDM540.250.4VDM

31、740.350.5IOL e 4 mA, VCC e MinDM740.250.4IIInput Current Max Input VoltageVCC e Max VI e 7VEnable T0.2mAClock, Clear0.2Load0.2Others0.1IIHHigh Level Input CurrentVCC e Max VI e 2.7VEnable T40mALoad40Clock, Clear40Others20IILLow Level Input CurrentVCC e Max VI e 0.4VEnable Tb0.8mAClock, Clearb0.8Load

32、b0.8Othersb0.4IOSShort Circuit Output CurrentVCC e Max (Note 2)DM54b20b100mADM74b20b100ICCHSupply Current with Outputs HighVCC e Max (Note 3)1831mAICCLSupply Current with Outputs LowVCC e Max (Note 4)1832mANote 1: All typicals are at VCC e 5V, TA e 25?C.Note 2: Not more than one output should be sho

33、rted at a time, and the duration should not exceed one second.Note 3: ICCH is measured with the load high, then again with the load low, with all other inputs high and all outputs open.Note 4: ICCL is measured with the clock input high, then again with the clock input low, with all other inputs low

34、and all outputs open.LS163 Switching Characteristicsat VCC e 5V and TA e 25?C (See Section 1 for Test Waveforms and Output Load)SymbolParameterFrom (Input) To (Output)RL e 2 kXUnitsCL e 15 pFCL e 50 pFMinMaxMinMaxfMAXMaximum Clock Frequency2520MHztPLHPropagation Delay Time Low to High Level OutputCl

35、ock to Ripple Carry2530nstPHLPropagation Delay Time High to Low Level OutputClock to Ripple Carry3038nstPLHPropagation Delay Time Low to High Level OutputClock to Any Q (Load High)2227nstPHLPropagation Delay Time High to Low Level OutputClock to Any Q (Load High)2738nsLS163 Switching Characteristics

36、at VCC e 5V and TA e 25?C (See Section 1 for Test Waveforms and Output Load) (Continued)SymbolParameterFrom (Input) To (Output)RL e 2 kXUnitsCL e 15 pFCL e 50 pFMinMaxMinMaxtPLHPropagation Delay Time Low to High Level OutputClock to Any Q (Load Low)2430nstPHLPropagation Delay Time High to Low Level

37、OutputClock to Any Q (Load Low)2738nstPLHPropagation Delay Time Low to High Level OutputEnable T to Ripple Carry1427nstPHLPropagation Delay Time High to Low Level OutputEnable T to Ripple Carry1527nstPHLPropagation Delay Time High to Low Level OutputClear to Any Q (Note 1)2845nsNote 1: The propagati

38、on delay clear to output is measured from the clock input transition.Logic DiagramLS163ATL/F/6397 2The LS161A is similar, however, the clear buffer is connected directly to the flip flops.Parameter Measurement InformationSwitching Time WaveformsTL/F/6397 3Note A: Theinputpulsesare supplied by genera

39、torshavingthefollowingcharacteristics: PRR s 1 MHz, dutycycle s 50%, ZOUT & 50X, tr s 10 ns, tf s 10 ns. Vary PRR to measure fMAX.Note B: Outputs QD and carry are tested at tna16 where tn is the bit time when all outputs are low.Note C: VREF e 1.5V.Switching Time WaveformsTL/F/6397 4NoteA:Theinputpu

40、lsesaresuppliedbygeneratorshavingthefollowingcharacteristics: PRR s 1MHz,duty cycles 50%, ZOUT & 50X,tr s 6 ns,tfs 6ns. Vary PRR to measure fMAX.Note B: Enable P and enable T setup times are measured at tna0.Note C: VREF e 1.3V.Timing DiagramLS161A, LS163A Synchronous Binary Counters Typical Clear,

41、Preset, Count and Inhibit SequencesTL/F/6397 5Sequence:(1) Clear outputs to zero(2) Preset to binary twelve(3) Count to thirteen, fourteen, fifteen, zero, one, and two(4) InhibitPhysical Dimensions inches (millimeters)Ceramic Leadless Chip Carrier Package (E) Order Numbers 54LS161ALMQB or 54LS163ALM

42、QBNS Package Number E20A16-Lead Ceramic Dual-In-Line Package (J)Order Numbers 54LS161ADMQB, 54LS163ADMQB, DM54LS161AJ or DM54LS163AJNS Package Number J16APhysical Dimensions inches (millimeters) (Continued)16-Lead Small Outline Molded Package (M) Order Number DM74LS161AM or DM74LS163AM NS Package Nu

43、mber M16A16-Lead Molded Dual-In-Line Package (N) Order Numbers DM74LS161AN, DM74LS163ANNS Package Number N16E54LS161A/DM54LS161A/DM74LS161A, 54LS163A/DM54LS163A/DM74LS163A Synchronous4-Bit Binary CountersNational Semiconductor Japan Ltd.Tel: 81-043-299-2309Fax: 81-043-299-2408National Semiconductor Hong Kong L