Low-k_Wire_Bonding.ppt

1、Low-k Wire Bonding,low-k低介電值 所謂low-k (低介電值）就是尋找介電常數較小的材料，以降低導線間電流的互相干擾作用，進而提升IC內導線傳輸功能。低介電係數絕緣體的界電係數通常被定義為值低於3。 由於電路信號傳遞的快慢是決定在電阻(R)與電容(C)乘積，RC乘積值越小，速度就越快。因此，降低電容值亦可改善傳輸速度。而電容值則與IC上金屬線間絕緣介電材料的介電係數K相關，K越小，電容值越小。 電容的大小，會跟平行板中的所放的介電物質有關： 其中 為電容率（permittivity）C= k E A/ d （A為平行板面積，d為平行板間距） 根據1837年法拉第發現，物

2、質的介電係數與其電容有關，他定義了介電常數。 一直作為金屬導線間絕緣材料的化二氧化矽(SiO2)，介電係數約為3.94.5間，然當製程不斷推進，二氧化矽己逐漸接近應用上的極限。 一般用於金屬導線間的介電材質層(Intermetal dielectric)，簡稱為IMD，其規格要求為高可靠度、低應力、製程簡單化、不易吸水和易於與金屬導線間作整合。 FSG (氟矽玻璃)係以二氧化矽材料為基礎，再加入氟，以降低電介薄膜的電容值(k)。,名詞解釋,銅製程到底跟一般製程有什麼地方不一樣? 隨著線寬的縮小，元件運算的速度便會受到電阻質的增加而顯著的下降特別是0.25微米世代以下。為了面對更密集的電路設計，

3、金屬材料如銅為一具有更低電阻材質的來取代鋁。 為了降低訊號傳遞的時間延遲，具有低電阻和低電容的材料，便因此應蘊而生。在低電阻部份，金屬銅由於具有高熔點，低電阻係數(1.7mW-cm) ，因而成為最有希望取代金屬鋁的金屬材質。另一方面，在低電容部份，電容C=e (A/d)，由於製程上及導線電阻的限制，使我們不考慮藉由幾何上的改變（例如：改變導線面積）來降低寄生的電容值。因此，具有低介電常數(low k)材質（可分為無機類及有機類聚合物）的研究，就成為主要的發展趨勢。,名詞解釋,Cu / low-k is the well-known solution to reduce signal delay

4、 and improve electrical performance for advanced IC. But the mechanical properties of Cu /low-k are poorer than Al/Si oxide combination. This study investigates the impact of packaging process and molding compound to achieve successful integration of Cu/low-k with assembly.,Introduction,Failure Mode

5、 Effect Analysis,Low-k dielectrics with poor characteristics result in novel challenges to assembly process.,Part I - Assembly Process Investigation (1) ( Die Saw Process ),The purpose of this study is to confirm if the conventional saw process could still be applied to low-k wafer.,Group 1 :,Group

6、2 :,Basic Information :,Low-k wafer : B company,Low-k dielectric : C type,Total / low-k layer : 7 / 1,Line width : 90nm,Laser + Blade Cut,Blade Cut,Experimental Design :,名詞解釋,關於laser cut,Normal cut,Laser+normal cut,Peeling in pads,Result & Discussion (1),Group 1 : Die saw by laser, no delamination w

7、as found after TCT 1000 with low stress EMC.,Conventional blade saw process cant prevent passivation peeling for low-k device. But the chips seal ring will stop the peeling. The blade saw process can be applied to low-k wafer if with low stress EMC.,Seal ring stop the passivation peeling,After TCT 1

8、000,After die saw,Conclusion,關於 molding compound vs. low k device,Evaluation of Molding Compound,The results showed that low CTE and low stress molding compounds are more suitable for low k chip package. (Coefficient thermal expansion),Six molding compounds were selected for the low k package evalua

9、tion and their properties are listed in table 2. After the package assembly, the test samples were subjected to precondition MSL3a test followed by TCT.,名詞解釋,Part I - Assembly Process Investigation (2) ( Wire Bond Process ),The purpose is to study any damage to bond pad for low-k structure with wire

10、 bonding process.,Test Vehicle:,Bond time: 15ms,USG current: 5062mA,Bond force: 1115mA,Gold wire : S xx 0.9mils,Capillary : M xx,Wire Bonder: K xx,Pad pitch: 60um,Pad open: 52*61um,Die size: 8.0 * 8.0mm,Package: BGA 37.5 * 37.5 552 I/O,1st bond graphical optimization:,Variable factors:,Bond temperat

11、ure: 160,CIC : (Contained Inner Chamfer) The CIC capillary contains most of the additional gold generated from first bond formation in its inner chamfer. Consistent, repeatable intermetallic coverage reduces pad peeling, cratering and non-stick occurrences.,名詞解釋,The capillaries produced with the ATL

12、AS material possess the following features: Higher fracture toughness supporting extremely small wall thickness Tighter tool tolerances increasing the process stability and robustness Smaller grain size enabling smoother surface finish and smaller hole diameter,名詞解釋,Wire Bond Result (2),Bonded ball

13、size :,The bonded ball diameter meet the target, and the shape shows acceptable.,Cross-section image :,The cross-section images show no ball bonding related damage on pad structure.,Wire Bond Result (2),IMC image :,The IMC coverage at 0hr, all are uniform.,Cratering test :,The bond pads after etchin

14、g. No oxide layer crack were observed.,All the quality check items, the performance are similar with Al/Si oxide wafer.,Mold condition :,Part I - Assembly Process Investigation (3) ( Molding Process ),Mold Temp: 175 C / 175 C,Transfer Pressure: 75 kg / cm2,Transfer time: 13.9 sec,Clamp force: 20 ton

15、s,Cure time: 120 sec,No Inner Delamination after Molding,Part II - Material Evaluation (EMC),In order to verify the effect of molding compound on WB-PBGA stress, there are two stages studies to investigate the stress distribution over die.,( Stage 1 3D Model ),Stag-1 Model :,- a quarter 3D model - d

16、ie size 8mmx8mm and 16mmx16mm - thermal loading conditions are 150 to -65 ,Die shear stress: 4.44kg/mm2,Die shear stress: 2.51kg/mm2,Die shear stress: 4.71kg/mm2,Die shear stress: 2.70kg/mm2,Die size: 8mmx8mm M/C: normal,Die size: 16mmx16mm M/C: normal,Die size: 8mmx8mm M/C: low stress,Die size: 16m

17、mx16mm M/C: low stress,Die central,Die central,Die central,Die central,1. Max. die shear stress is located at die corner. (Please see attached plots) 2. Low-stress molding compound has lower die corner shear stress.,Simulation Result,( Stage 1 3D Model ),Stag-2 Model :,- a half 2D model - die size 8

18、mmx8mm and 16mmx16mm - thermal loading condition is 150 to -65 - low-k structure is added above the die top.,Die size: 8mmx8mm,Die size: 16mmx16mm,( Stage 2 2D Model ),1. Max. die shear stress is also located at bottom layers between low-k and metal layers near silicon die. 2. Low-stress molding com

19、pound has lower die corner shear stress.,Simulation Result,( Stage 2 2D Model ),1. Low stress molding compound effectively reduces the die corner shear stress for both the die size of 8mmx8mm and 16mmx16mm to prevent the low-k layer peeling. 2. In stage 2 study, the max. shear stress is located at t

20、he edge of low-k bottom layer and silicon die. There is consistency between failure mode and simulation result.,Die,Compound,Simulation Result,Part III Wafer Fabrication (Cut Street Structure),By TCT and SAT inspection, structure 2 & 3 have lower defect rate of delamination. The structure 2 & 3 effectively hold the metal layer and fixed SiO2, thus indicated t