DDR3-SPD-附中文翻译

1、Understanding DDR3 Serial Presence Detect (SPD) Table Tuesday, July 17, 2007 IntroductionSince I wrote 揢nderstanding DDR Serial Presence Detect (SPD) Table?in 2003, I have been getting a lot a feedback from readers. I added 揢nderstanding DDR2 Serial Presence Detect (SPD) Table?in 2006. Some of you t

2、old me that you are using these articles to train your employees and to introduce the mysteries SPD concept to your customers. I feel honored by your responses. Lately, CST has started shipment of a DDR3 EZ Programmer. Since the DD3 DIMM is introduced recently, I think this is the time to add an art

3、icle for the DDR3 SPD Table. Due to the many more years of development, the DD3 SPD table has definitely got more sophisticated than the original DDR and DDR2 SPD table. Your attention is required to understand and follow through. I will try to use as much layman language as I can to accommodate you

4、 all.Serial Presence Detect (SPD) data is probably the most misunderstood subject in the memory module industry. Most people only know it as the little Eeprom device on the DIMM that often kept the module from working properly in the computer. On the contrary, it is quite the opposite. The SPD data

5、actually provide vital information to the system Bios to keep the system working in optimal condition with the memory DIMM. This article attempts to guide you through the construction of an SPD table with 揟urbo-Tax?type of multiple choices questions. I hope you抣l find it interesting and useful. Samp

6、le Jedec Standard SPD Data TableByte 0Number of Serial PD Bytes Written/ SPD Device Size/ CRC Coverage （写入的SPD字节数/EERPOM总字节数/CRC覆盖字节范围）Bit 3 to Bit 0 describes the total size of the serial memory actually used in the EEprom for the Serial Presence Detect data. Bit 6 to Bit 4 describes the number of

7、bytes available in the EEprom device, usually 128byte or 256 byte. On top of that, Bit 7 indicates whether the unique module identifier covered by the CRC encoded on bytes 126 and 127 is based on (0-116byte) or based on (0-125byte). (When CST EZ-SPD Programmer is used: Simply select items from 3 tab

8、les and automatically calculate the final hex number)The most common one used is:Total SPD Bye = 256CRC Coverage = 0-116ByteSPD Byte used = 176 ByteResulting code is92hByte 1SPD Revision （SPD规范版本）Version 0.0 00hRevision 0.5 05hRevision 1.0 10hRevision 1.1 11hRevision 1.2 12hByte 2 （DRAM类型）DRAM Devic

9、e Type This refers to the DRAM type. In this case, we are only dealing with DDR3 SDRAM.DDR3 SDRAM: 0Bh Byte 3Module Type （内存module类型）This relates to the physical size, and category of memory module.Undefined 00hRDIMM (Registered Long DIMM) 01hUDIMM (Unbuffered Long DIMM) 02hSODIMM (Small Outline DIM

10、M) 03hByte 4 SDRAM Density and Banks （DRAM容量和内部bank数）This byte defines the total density of the DDR3 SDRAM, in bits, and the number of internal banks into which the memory array is divided.Presently all DDR3 have 8 internal banks. SDRAM Chip Size 512Mb 01h1Gb 02h2Gb 03h4Gb 04hByte 5SDRAM Addressing

11、（DRAM行列地址线数目）This byte describes the row addressing and column addressing in the SDRAM Device.512Mb chips 13 Row X 10 Column 09h 13 Row X 12 Column 0Bh12 Row X 10 Column 01h1Gb chips 14 Row X 10 Column 11h14 Row X 12 Column 13h13 Row X 10 Column 09h2Gb chips 15Row X 10 Column 19h15 Row X 12 Column 1

12、Bh14 Row X 10 Column11hByte 6 （预留）Reserved 00hByte 7 （内存module架构）Module OrganizationThis byte describes the organization of the SDRAM module; the number of Ranks and the Device Width of each DRAM(When CST EZ-SPD Programmer is used: Simply select number of Ranks and Device Width. It automatically cal

13、culate final hex number)1 Rank module using X8 chips 01h2 Rank module using X8 chips09h1 Rank module using X4 chips00h2 Rank module using X4 chips08h4 Rank module using X8 chips 19h4 Rank module using X4chips18h1 Rank module using X16 chips02h2 Rank module using X16 chips0AhByte 8Module Memory Bus W

14、idth （内存总位宽）This refers to the primary bus width of the module plus the additional with provided by ECC16bit01h32bit04h64bit (no parity)03h64bit + ECC (72bit) 0BhByte 9Fine timebase (FTB) Dividend / Divisor （时基）This byte defines a value in picoseconds that represents the fundamental timebase for fin

15、e grain timing calculations. This value is used as a multiplier for formulating subsequent timing parameters. The granularity in picoseconds is derived from Dividend being divided by the Divisor.Granularity:2.5ps52h5ps55hByte 10Medium Timebase (MTB) Dividend （时间参数编码所用时基的分子）Byte 11Medium Timebase (MT

16、B) Divisor（时间参数编码所用时基的分母）These byte defines a value in nanoseconds that represents the fundamental timebase for medium grain timing calculations. This value is used as a multiplier for formulating subsequent timing parameters. The two byte forms the Dividend and the Divisor to determine the granular

17、ity of the medium timebase.Granularity 0.125ns Byte 10 01h Byte 11 08h 0.0625ns Byte 10 01h Byte 11 0FhByte 12Minimum SDRAM Cycle Time (tCK min) （DRAM颗粒最小时钟周期）This byte describes the minimum cycle time for the module in medium timebase (MTB) units.For MTB granularity = 0.125ns (Byte 10 and Byte 11)D

18、DR3 400Mhz clock (800data rate) 14hDDR3 533Mhz clock (1066data rate) 0FhDDR3 667Mhz clock (1333data rate) 0ChDDR3 800Mhz clock (1600data rate) 0AhByte 13 （预留）Reserved 00hByte 14CAS Latencies Supported, Low Byte （支持CL值范围，低位字节）(When CST EZ-SPD Programmer is used: Simply select all latencies supported

19、from table. Automatically calculate the hi and low byte hex value base on binary number)Latency 5.6 supported06hLatency 6 supported04hLatency 6,7 supported0ChLatency 5, 6, 7, 8 supported1EhByte 15 CAS Latencies Supported, High Byte 00h （支持CL值范围，高位字节）Byte 16Minimum CAS Latency Time (tAAmin) （CAS延迟平均时

20、间tAAmin）Minimum CAS Latency based on medium timebase (MTB) units. tAAmin can be read off SDRAM data sheet.Based on medium timebase of 0.125nstAAmin 12.5nsDDR3-800D 64h 15nsDDR3-800E 78h11.25nsDDR3-1066E 5Ah13.125nsDDR3-1066F 69h15nsDDR3-1066G 78h10.5nsDDR3-1333F 54h12nsDDR3-1333G 60h13.5ns DDR3-1333

21、H 6Ch15ns DDR3-1333J 78h10ns DDR3-1600G 50h11.25ns DDR3-1600H 5Ah12.5 ns DDR3-1600J 64h13.75ns DDR3-1600K 6EhByte 17Minimum Write Recovery Time (tWRmin) （最小写恢复时间tWRmin）This byte defines the minimum SDRAM write recovery time in medium timebase (MTB) units. This value is read from the DDR3 SDRAM data

22、sheet.Based on medium timebase of 0.125nstWR min 15ns 78h12ns 60h16ns 80hByte 18Minimum RAS# to CAS# Delay time (tRCDmin) （RAS到CAS的延迟时间tRCDmin）This byte defines the minimum SDRAM RAS# to CAS# Delay in (MTB) unitsBased on medium timebase of 0.125nstRCD min 12.5nsDDR3-800D 64h 15nsDDR3-800E 78h11.25ns

23、DDR3-1066E 5Ah 13.125nsDDR3-1066F 69h 15nsDDR3-1066G 78h10.5nsDDR3-1333F 54h12nsDDR3-1333G 60h15nsDDR3-1333J 78h10nsDDR3-1600G 50h11.25ns DDR3-1600H 5Ah12.5 ns DDR3-1600J 64h13.75ns DDR3-1600K 6EhByte 19Minimum Row Active to Row Active Delay time (tRRDmin) （ROW激活命令间隔时间tRRDmin）This byte defines the m

24、inimum SDRAM Row Active to Row Active Delay in (MTB) units. This can be read from the SDRAM data sheet.Based on medium timebase of 0.125nstRRD min 6.0 ns30h 7.5 ns3Ch10 ns50hByte 20Minimum Row Precharge Delay Time (tRPmin) （预充电precharge延迟时间tRPmin）This byte defines the minimum SDRAM Row Precharge Del

25、ay in (MTB) units. This can be read from the SDRAM data sheet.Based on medium timebase of 0.125nstRP min 12.5nsDDR3-800D 64h 15nsDDR3-800E 78h13.125ns DDR3-1066F 69h15nsDDR3-1066G 78h10.5nsDDR3-1333F 54h12nsDDR3-1333G 60h13.5nsDDR3-1333H 6Ch15ns DDR3-1333J 78h10ns DDR3-1600G 50h11.25ns DDR3-1600H 5A

26、h12.5 ns DDR3-1600J 64h13.75ns DDR3-1600K 6EhByte 21Upper Nibbles for tRAS and tRC （tRAS和tRC时间的高位字节）This byte makes up the MSB (upper 4 bits) of the tRAS (bits 3-0) and tRC (bits 7-4) for Byte 22 (tRAS lower byte) and Byte 23 (tRC lower byte). They are in (MTB) units. Based on medium timebase of 0.1

27、25nsThese nibbles represents the value of 256 (in MTB units) for both the tRAS and tRC upper nibble. Therefore, the value is always11hByte 22Minimum Active to Precharge Delay Time (tRAS min), Least Significant Byte（激活到预充电延迟时间tRAS的低位字节）This byte is the lower 8 bits of the 12 bit tRAS value. It is rep

28、resented in MTB units. The tRAS value can be read from the SDRAM data sheet. Based on medium timebase of 0.125nstRAS min 37.5ns DDR3-800D 2Ch 37.5ns DDR3-800E 2Ch37.5ns DDR3-1066E 2Ch37.5ns DDR3-1066F 2Ch37.5ns DDR3-1066G 2Ch36ns DDR3-1333F 20h36ns DDR3-1333G 20h36ns DDR3-1333H 20h36ns DDR3-1333J 20

29、h35ns DDR3-1600G 18h35ns DDR3-1600H 18h35ns DDR3-1600J 18h35ns DDR3-1600K 18hByte 23Minimum Active to Active Refresh Delay Time (tRC min), Least Significant Byte（激活到激活/刷新的延迟时间tRCmin的低位字节）This byte is the lower 8 bits of the 12 bit tRC value. It is represented in MTB units. The tRC value can be read

30、from the SDRAM data sheet. Based on medium timebase of 0.125nstRC min 50ns DDR3-800D 90h 52.5ns DDR3-800E A4h48.75ns DDR3-1066E 86h50.625ns DDR3-1066F 95h52.5ns DDR3-1066G A4h46.5ns DDR3-1333F 74h48ns DDR3-1333G 80h49.5ns DDR3-1333H 8Ch51ns DDR3-1333J 98h45ns DDR3-1600G 68h46.25ns DDR3-1600H 72h47.5

31、ns DDR3-1600J 7Ch48.75ns DDR3-1600K 86hByte 24Minimum Refresh Recovery Delay Time (tRFCmin), Least Significant Byte（刷新恢复延迟时间tRFCmin的低位字节）Byte 25Minimum Refresh Recovery Delay Time (tRFCmin), Most Significant Byte （刷新恢复延迟时间tRFCmin的高位字节）These two Byes forms a 16 bit value representing the tRFC value i

32、n MTB units. Based on medium timebase of 0.125nstRFC min for 512Mb chip 90ns Byte 24 D0h Byte 25 02hfor 1Gb chip 110ns Byte 24 70h Byte 25 03hfor 2Gb chip 160ns Byte 24 00h Byte 25 05hByte 26 （写到读命令延迟时间tWTRmin）Minimum Internal Write to Read Command Delay time (tWTRmin)This byte defines the minimum S

33、DRAM Internal Write to Read Delay Time in MTB units. This value is read off the data sheet.Based on medium timebase of 0.125nstWTR min 7.5ns is for all DDR3 speed bins 3Ch Byte 27 （读到预充命令延迟时间tRTP）Minimum Internal Read to Precharg Command Delay time (tRTPmin)This byte defines the minimum SDRAM Intern

34、al Read to Precharge Command Delay Time in MTB units. This value is read off the data sheet.Based on medium timebase of 0.125nstRTP min 7.5ns is for all DDR3 speed bins 3Ch Byte 28 （4激活命令窗口最小时间tFAWmin的高位字节）Upper Nibbles for tFAWThis byte makes up the most significant bit value (upper 4 bits) of the

35、tFAW (bits 3-0). They are in (MTB) units. This value is read off the SDRAM data sheet. Based on medium timebase of 0.125nsFor tFAW value of 32ns or higher, the hex value for this byte is 01hFor all tFAW value less than 32ns, the hex value for this byte is 00hByte 29 （4激活命令窗口最小时间tFAWmin的低位字节）Minimum

36、Four Activate Window Delay Time (tFAWmin), Least Significant ByteThis works with Byte 28 to form a 12-bit value which defines the minimum SDRAM Four Activate Window Delay Time in MTB units. This data is available on the SDRAM data sheet.Based on medium timebase of 0.125nstFAW min 40.0ns DDR3-800, 1K

37、 page size 40h50.0ns DDR3-800, 2K page size 90h37.5ns DDR3-1066, 1K page size 2Ch50.0ns DDR3-1066, 2K page size 90h30.0ns DDR3-1333, 1K page size F0h45.0ns DDR3-1333, 2K page size 68h30.0ns DDR3-1600, 1K page size F0h40.0ns DDR3-1600, 2K page size 40hByte 30 （DRAM颗粒可选特色）SDRAM Optional features This

38、byte defines the optional drive strengths supported by the SDRAMs on this module. This information can be found from the SDRAM data sheet.RZQ/6 supported RZQ/7 supported 03hRZQ/6 supported RZQ/7 not supported 01hRZQ/6 not supported RZQ/7 supported 02hByte 31 （DRAM热控和刷新功能）SDRAM thermal and refresh op

39、tionsThis byte describes the module抯 supported operating temperature ranges and refresh options. These values come from the DDR3 SDRAM data sheet. The information includes On-die Thermal sensor support, ASR Refresh support, 1X or 2X Temperature Refresh Rate support as well as the Extended Temperatur

40、e Range.(When CST EZ-SPD Programmer is used: Simply select all supported options from table. It automatically calculate the hex value based on the 2 byte binary number)Byte 32 Module thermal sensor （模组热传感集成）未使用热感 00h使用热感 80hByte 33 DRAM内核数目单核 00h非单核 80hByte 3459 预留Reserved, General Section 00hByte 6

41、0Module Nominal Height 内存模组高度Under or equal 15mm 00hBetween 15 and 16mm 01hBetween 16 and 17mm 02hBetween 17 and 18mm 03hBetween 18 and 19mm 04hBetween 19 and 20mm 05hBetween 20 and 21mm 06hBetween 21 and 22mm 07hBetween 22 and 23mm 08hBetween 23 and 24mm 09hBetween 24 and 25mm 0AhBetween 25 and 26m

42、m 0BhBetween 26 and 27mm 0ChBetween 27 and 28mm 0DhBetween 28 and 29mm 0EhBetween 29 and 30mm 0FhBetween 30 and 31mm 10hBetween 31 and 32mm 11hBetween 32 and 33mm 12hBetween 33 and 34mm 13hBetween 34 and 35mm 14hBetween 35 and 36mm 15hBetween 36 and 37mm 16hBetween 37 and 38mm 17hBetween 38 and 39mm

43、 18hBetween 39 and 40mm 19hBetween 40 and 41mm 1AhBetween 41 and 42mm 1BhBetween 42 and 43mm 1ChBetween 43 and 44mm 1DhBetween 44 and 45mm 1EhOver 45mm1FhByte 61Module Mechanical Maximum Thickness 内存最大厚度This byte defines the maximum thickness in millimeters of the fully assembled module including he

44、at spreaders and any other components. It is in two parts; the front thickness (from PCB surface) and the back thickness (from PCB surface).(When CST EZ-SPD Programmer is used: Simply selected by number between 1-15mm for front thickness and by number between 1-15mm for back thickness. Program autom

45、atically converts these thickness number into 2 byte hex code.)Smaller or equal to 1mm on both front and back 00h1 to 2 mm on both front and back11h2 to 3 mm on both front and back22h3 to 4 mm on both front and back33h2 mm on front 1 mm max on back 01h3 mm on front 1 mm max on back02h4 mm on front 1 mm max on back03h Byte 62Reference Raw Card Used 使用的Raw card类型This Byt