计算机组织与结构：版7-16_Control Unit

1、1/45,William Stallings Computer Organization and Architecture7th Edition,Chapter 16 Control Unit Operation,2/50,Key Terms,Control bus Control path Control signal Control unit Hardwired implementation Microoperations Control unit operation,3/50,Micro-Operations,A computer executes a program Fetch/exe

2、cute cycle Each cycle has a number of steps see pipelining Called micro-operations Each step does very little Atomic operation of CPU,4/50,Constituent Elements of Program Execution,5/50,Fetch - 4 Registers,Memory Address Register (MAR) Connected to address bus Specifies address for read or write op

3、Memory Buffer Register (MBR) Connected to data bus Holds data to write or last data read Program Counter (PC) Holds address of next instruction to be fetched Instruction Register (IR) Holds last instruction fetched,6/50,Fetch Sequence,Address of next instruction is in PC Address (MAR) is placed on a

4、ddress bus Control unit issues READ command Result (data from memory) appears on data bus Data from data bus copied into MBR PC incremented by 1 (in parallel with data fetch from memory) Data (instruction) moved from MBR to IR MBR is now free for further data fetches,7/50,Data Flow (Fetch Diagram),8

5、/50,Fetch Sequence (symbolic),t1:MAR - (PC) t2:MBR - (memory) PC - (PC) +1 t3:IR - (MBR) (tx = time unit/clock cycle) or t1:MAR - (PC) t2:MBR - (memory) t3:PC - (PC) +1 IR - (MBR),9/50,Rules for Clock Cycle Grouping,Proper sequence must be followed MAR - (PC) must precede MBR - (memory) Conflicts mu

6、st be avoided Must not read & write same register at same time MBR - (memory) & IR - (MBR) must not be in same cycle Also: PC - (PC) +1 involves addition Use ALU May need additional micro-operations,10/50,Data Flow (Indirect Diagram),11/50,Indirect Cycle,MAR - (IRaddress) - address field of IR MBR -

7、 (memory) IRaddress - (MBRaddress) MBR contains an address IR is now in same state as if direct addressing had been used (What does this say about IR size?),12/50,Data Flow (Indirect Diagram),13/50,Data Flow (Interrupt Diagram),(2),(3),(1),(4),(5),14/50,Interrupt Cycle,t1:MBR -(PC) t2:MAR - save-add

8、ress PC - routine-address t3:memory - (MBR) This is a minimum May be additional micro-ops to get addresses N.B. saving context is done by interrupt handler routine, not micro-ops,15/50,Execute Cycle (ADD),Different for each instruction e.g. ADD R1,X - add the contents of location X to Register 1 , r

9、esult in R1 t1:MAR - (IRaddress) t2:MBR - (memory) t3:R1 - R1 + (MBR) Note no overlap of micro-operations,16/50,Execute Cycle (ISZ),ISZ X - increment and skip if zero t1:MAR - (IRaddress) t2:MBR - (memory) t3:MBR - (MBR) + 1 t4:memory - (MBR) if (MBR) = 0 then PC - (PC) + 1 Notes: if is a single mic

10、ro-operation Micro-operations done during t4,17/50,Execute Cycle (BSA),BSA X - Branch and save address Address of instruction following BSA is saved in X Execution continues from X+1 t1:MAR - (IRaddress) MBR - (PC) t2:PC - (IRaddress) memory - (MBR) t3:PC - (PC) + 1,18/50,Instruction Cycle,Each phas

11、e decomposed into sequence of elementary micro-operations E.g. fetch, indirect, and interrupt cycles Execute cycle One sequence of micro-operations for each opcode Need to tie sequences together Assume new 2-bit register Instruction cycle code (ICC) designates which part of cycle processor is in 00:

12、 Fetch 01: Indirect 10: Execute 11: Interrupt,19/50,Flowchart for Instruction Cycle,20/50,Functional Requirements,Define basic elements of processor Describe micro-operations processor performs Determine functions control unit must perform,21/50,Basic Elements of Processor,ALU Registers Internal dat

13、a pahs External data paths Control Unit,22/50,Types of Micro-operation,Transfer data between registers Transfer data from register to external Transfer data from external to register Perform arithmetic or logical ops,23/50,Functions of Control Unit,Sequencing Causing the CPU to step through a series

14、 of micro-operations Execution Causing the performance of each micro-op This is done using Control Signals,24/50,Control Signals,Clock One micro-instruction (or set of parallel micro-instructions) per clock cycle Instruction register Op-code for current instruction Determines which micro-instruction

15、s are performed Flags State of CPU Results of previous operations From control bus Interrupts Acknowledgements,25/50,Model of Control Unit,26/50,Control Signals - output,Within CPU Cause data movement Activate specific functions Via control bus To memory To I/O modules,27/50,Example Control Signal S

16、equence - Fetch,MAR - (PC) Control unit activates signal to open gates between PC and MAR MBR - (memory) Open gates between MAR and address bus Memory read control signal Open gates between data bus and MBR,28/50,Data Paths and Control Signals,29/50,Internal Organization,Usually a single internal bu

17、s Gates control movement of data onto and off the bus Control signals control data transfer to and from external systems bus Temporary registers needed for proper operation of ALU,30/50,Data Paths and Control Signals,Execute Cycle (ADD) Execute Cycle (ISZ) Execute Cycle (BSA),31/50,Internal Organiza

18、tion,Usually a single internal bus Gates control movement of data onto and off the bus Control signals control data transfer to and from external systems bus Temporary registers needed for proper operation of ALU t1:MAR(IR(address) t2:MBRMemory t3:Y(MBR) t4:Z(AC)+(Y) t5:AC(Z),32/50,CPU with Internal

19、 Bus,c1,c2,c10,c7,c8,c9,c11,c3,c4,c5,c6,33/50,Intel 8085 CPU Block Diagram,34/50,Intel 8085 Pin Configuration,35/50,Intel 8085 OUT InstructionTiming Diagram,36/50,Hardwired Implementation (1),Control unit inputs Flags and control bus Each bit means something Instruction register Op-code causes diffe

20、rent control signals for each different instruction Unique logic for each op-code Decoder takes encoded input and produces single output n binary inputs and 2n outputs,37/50,Hardwired Implementation (2),Clock Repetitive sequence of pulses Useful for measuring duration of micro-ops Must be long enoug

21、h to allow signal propagation Different control signals at different times within instruction cycle Need a counter with different control signals for t1, t2 etc.,38/50,Control Unit with Decoded Inputs,PQ=00 Fetch Cycle PQ=01 Indirect Cycle PQ=10 Execute Cycle PQ=11 Interrupt Cycle,39/50,Control Unit

22、 with Decoded Inputs,40/50,Problems With Hard Wired Designs,Complex sequencing & micro-operation logic Difficult to design and test Inflexible design Difficult to add new instructions,41/50,Required Reading,Stallings chapter 16,42/50,计算机结构与逻辑设计 黄正瑾编著,第七章 控制单元 7.1 计算机中的寄存器及其控制信号 7.2 指令的执行过程 7.3 控制电路的

23、硬件结构 7.4 其他类型指令的执行过程 7.5 微程序控制方式 7.6 全硬件数字系统控制器的设计,43/50,P291 7.5 微程序控制方式,每条指令的执行过程可以认为是按照一定的“微程序”进行的，这个“微程序”可以用硬件实现，也可以用软件实现。 所谓微程序控制，就是将执行指令的微程序用一条条二进制代码编写的微指令组成，成为真正意义上的程序，并用此程序来控制指令的执行。,44/50,图 7.9 微程序控制系统框图,IAR: 微指令地址寄存器 (uPC) OP: 刚才存在操作码寄存器中的数据,45/50,图7.10所示是某个计算机微程序控制器中的ROM，它的每条指令的解释与表7.4相同。现在以此ROM为例，说明微程序系统中指令的执行情况。 设起始时微指令地址寄存器IAR中的数据为0，计算机运行后从ROM中取的第一条微指令是0号微指令，其代码为0000 0000 0000 0010 0000 0010 00，它所