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毕 业 设 计（论 文）任 务 书1本毕业设计（论文）课题应达到的目的： 通过毕业设计，使学生能够通过综合运用所学的专业知识为相关行业的应用需求提供解决方案。在此过程中，提高学生提出问题、分析问题和解决问题的能力，锻炼学生的实践动手能力。具体包括以下几方面： 1. 综合运用专业理论知识分析解决实际问题的能力。 2. 针对研究对象进行调查研究以及查阅检索相关中外文献的能力。 3. 定性与定量相结合的独立研究与论证的能力。 4. 制定设计方案和实验方案、仪器设备的选型、安装、调试以及采集和分析处理实验数据的能力。 5. 使用科研工具包括使用专业设备、计算机和专业软件的能力。 6. 撰写设计说明书和论文的能力。 2本毕业设计（论文）课题任务的内容和要求（包括原始数据、技术要求、工作要求等）： 1. 本设计应完成公共自行车智能管理系统的设计，含以下两个部分的设计内容： 一是自行车节点的设计，实现对自行车状态的监控，主要包括：用户身份识别、电子车锁、胎压监测、实时定位、里程计等，相关信息由GPRS网络发送至管理中心。二是中心管理系统，主要用于对自行车节点上报的信息进行统一处理和存储，同时也支持中心主动对各节点的状态进行查询。 2按时完成开题报告书。 3按时完成毕业设计外文参考资料。 4能够圆满完成指导老师布置的课题任务，设计方案合理，能够体现一定的创新性。 5按时参加答辩，在答辩前各项规定的资料要齐全。 毕 业 设 计（论 文）任 务 书3对本毕业设计（论文）课题成果的要求包括图表、实物等硬件要求： 1. 按期完成一篇符合金陵科技学院论文规范的毕业设计说明书（毕业论文），能详细说明设计步骤和思路； 2. 能有结构完整，合理可靠的设计方案； 3. 能够通过情景模拟和实物演示对毕设要求中所涉及的功能进行验证。 4主要参考文献： 1 胡宝兴,贾颖莲,姜伟. 电动自行车用无刷直流电动机控制器的设计J. 微特电机. 2006(12) 2 胡宝兴. 基于DSP的电动自行车用无刷直流电机控制系统的研究D. 浙江工业大学 2005 3 寇治国. 基于TMS320F28035的电动自行车控制器的设计D. 杭州电子科技大学 2011 4 邢少芳. 智能交通监控系统中的运动目标检测研究D. 天津大学 2012 5 黄德宝. 智能交通监控系统中运动目标的检测与预警技术D. 哈尔滨工程大学 2012 6 孙元敏. 基于DSP的数据采集处理系统的设计与实现D. 山东大学 2008 7 向文溢. 基于DSP的多通道信号采集分析系统的研究与应用D. 武汉理工大学 2010 8 孟祥儒. 基于DSP的数据采集处理及显示系统D. 中国科学技术大学 2009 9 刘芳. 基于DSP的组合导航系统研究D. 南京理工大学 2007 10 宋东清. 基于DSP的导航计算机系统设计D. 哈尔滨工程大学 2007 11 徐俊仕. 基于嵌入式Linux的车载GPS导航系统设计与实现D. 西北工业大学 2007 12 张杰. GPS导航系统L2C信号的跟踪算法及其实现研究D. 南京邮电大学 2014 13 汪亚东. 基于GPS的嵌入式公交自动报站系统的研究D. 西安科技大学 2008 14 高瑞昌,孙昌国. DSP在电机测速中的应用J. 今日电子. 2004(02) 15 张俊龙. 基于DSP的短距离无线数据通信技术研究D. 哈尔滨工程大学 2004 16 王娟. 单片机串口通信在物理实验中的应用J. 科技创新导报. 2008(25) 17 苏奎峰，吕强，常天庆，张永秀.TMS320X281x DSP原理及C程序开发.北京：北京航空航天大学出版社，2008 毕 业 设 计（论 文）任 务 书5本毕业设计（论文）课题工作进度计划：2015.11.102015.12.13 调研、收集相关资料、对学生进行初步辅导，拟题、选题、填写任务书。 2015.12.152015.12.31 学生查看任务书，为毕业设计的顺利完成，进行前期准备。 2016.01.092016.04.05 学生在指导教师的具体指导下进行毕业设计创作；拟定论文提纲或设计说明书（下称文档）提纲；撰写及提交开题报告、外文参考资料及译文、论文大纲。 2016.04.062016.04.10 提交中期课题完成情况报告给指导教师审阅；各专业组织中期检查（含毕业设计成果验收检查）。 2016.04.112016.05.10 进行毕业设计文档撰写。 2016.05.142016.05.29 毕业设计（论文）小组答辩，完成毕业设计的成绩录入 2016.05.302016.06.07 根据答辩情况修改毕业设计（论文）的相关材料，并在毕业设计（论文）管理系统中上传最终稿，并且上交纸质稿。 2016.06.072016.06.30 各系提交本届毕业设计（论文）的工作书面总结及相关材料。 所在专业审查意见：通过负责人： 2015 年 12 月21 日 毕 业 设 计（论文） 开 题 报 告 1结合毕业设计（论文）课题情况，根据所查阅的文献资料，每人撰写不少于1000字左右的文献综述： 课题综述： 本课题是为了解决公共自行车使用过程中，市民对自行车随意停放甚至丢失相关部门难以管理等问题。该系统同时在自行车使用过程中提供相应的实时速度检测，骑行时间，总里程，气温等性能。为了解决随意停放问题，本系统采用GPS定位功能，对自行车当前位置进行检测，使相关部门合理调控便于市民更好的使用公共自行车。我国公共自行车最早出现于2005年的北京，当时只是一些个体户经营的自行车出租服务，还没有引起人们的注意。直到2007年7月15日，全球最著名的户外广告公司法国德高集团在巴黎率先推出了“单车自由骑”自行车租赁服务，倡导环保出行，公共自行车的概念才开始进入人们的视野。自杭州、武汉等城市在国内率先启动便民自行车系统建设后，几年时间，各地纷纷效仿，公共自行车成为社会服务热点。据不完全了解，目前在全国推广或试点的有包括北京、上海、广州、深圳在内的大中城市38个。其中，杭州、武汉在规模、效应、运作模式等方面的探索，名列前茅。目前，公共自行车项目已在全国多个城市迅速扩展，被公众广泛接受，部分城市的公共自行车项目还被纳入到国家“城市步行和自行车交通系统示范项目”,正逐步形成我国未来公共交通系统的一种新模式。当前，我国公共自行车发展迅速，在短时间内取得了一定的成功。但要看到，公共自行车租赁服务系统还存在诸多问题亟待解决，如提供自行车的数量和租赁的站点少，易丢失，市民随意停放，布点不科学，使用不便和系统故障等问题。本课题采用GPS定位系统对公共自行车实时监测，提供位置信息方便相关部门管理与调度。同时提供友好的人机交互界面便于用户使用。GPS实时定位系统在公共自行车交通领域的应用实现了公共自行车24小时无人值守，本地借车异地还车，提高了车辆流转和配置的效率，方便广大市民的使用并降低了运营中的人工成本，是“智慧交通”和“智慧城市”的重要体现。 本文主要用的文献：1 胡宝兴,贾颖莲,姜伟. 电动自行车用无刷直流电动机控制器的设计J. 微特电机. 2006(12)2 胡宝兴. 基于DSP的电动自行车用无刷直流电机控制系统的研究D. 浙江工业大学 20053 寇治国. 基于TMS320F28035的电动自行车控制器的设计D. 杭州电子科技大学 20114 邢少芳. 智能交通监控系统中的运动目标检测研究D. 天津大学 20125 黄德宝. 智能交通监控系统中运动目标的检测与预警技术D. 哈尔滨工程大学 20126 孙元敏. 基于DSP的数据采集处理系统的设计与实现D. 山东大学 20087 向文溢. 基于DSP的多通道信号采集分析系统的研究与应用D. 武汉理工大学 20108 孟祥儒. 基于DSP的数据采集处理及显示系统D. 中国科学技术大学 20099 刘芳. 基于DSP的组合导航系统研究D. 南京理工大学 200710 宋东清. 基于DSP的导航计算机系统设计D. 哈尔滨工程大学 200711 徐俊仕. 基于嵌入式Linux的车载GPS导航系统设计与实现D. 西北工业大学 200712 张杰. GPS导航系统L2C信号的跟踪算法及其实现研究D. 南京邮电大学 201413 汪亚东. 基于GPS的嵌入式公交自动报站系统的研究D. 西安科技大学 200814 高瑞昌,孙昌国. DSP在电机测速中的应用J. 今日电子. 2004(02)15 张俊龙. 基于DSP的短距离无线数据通信技术研究D. 哈尔滨工程大学 200416 王娟. 单片机串口通信在物理实验中的应用J. 科技创新导报. 2008(25)毕 业 设 计（论文） 开 题 报 告 2本课题要研究或解决的问题和拟采用的研究手段（途径）： 本课题要解决的问题：1.如何检测当前车速？2.如何将实时信息送到上位机？3.GPS定位的准确性如何提高？设计途径:1.一般常用的方法有测速发电机，霍尔传感器，光电编码器。通过捕获单元CAP捕获霍尔元件发出脉冲实现速度检测。2.采用异步通信通过串行通信接口SCI将信息送给上位机3.使用相关芯片提高定位准确性毕 业 设 计（论文） 开 题 报 告 指导教师意见：1对“文献综述”的评语：文献综述较为详细的介绍了公共自行车管理系统的发展，以及其在社会生产、活动中的重要意义。提出了该管理系统的结构和相关技术特点，对课题所涉内容的理解较为深刻。 2对本课题的深度、广度及工作量的意见和对设计（论文）结果的预测：本课题拟设计一套针对公共自行车的智能管理系统，主要涉及自行车状态监控、车体定位、租借功能、防偷盗功能和后台信息管理系统的设计。工作量较大，难度适中。 3.是否同意开题： 同意 不同意 指导教师： 2016 年 03 月 29 日所在专业审查意见：同意 负责人： 2016 年 03 月 30 日Throughout this article,DSP refers to the VLSI (very large-scale integration) processor component. Therefore what special demands in digital signal processing make a DSP different from another programmable processor In other words,what makes a DSP a DSP?The Realtime Requirement. The essential application characteristic driving DSP architecture is the requirement to process realtime signals.Realtime means that the signal represents physical or “real” events. DSPs are designed to process realtime signals and must therefore be able to process the samples at the rate they are generated and arrive. Adding significant delay,or latency,to the output can be objectionable. While high realtime rates often demand that DSPs be “fast” ,fast and realtime are different concepts.For example simulations of VLSI designs must be fastthe faster the betterbut the application doesnt fail if the simulator completes a little slower. Conversely a realtimeapplication need not be fastfor example,a hospital room heart monitor doesnt need to be fast (30-Hz sample rate) but does need to be realtime; it would be disastrous if the processing of a sample took so long that after a few hours the monitor was displaying five-minute-old data. Not all digital signal processing applications require realtime processing.Many applications are performed offline. For instance encoding high-fidelity audio for mastering CD-ROMs uses sophisticated digital signal pro-cessing algorithms but the work isnt done in realtime.Consequently a DSP isnt requiredany old processor fast enough for the engineer to get home for dinner will do. To summarize, the most important distinguish-ing characteristic of DSPs is that they process realtime signalsthe signals can be fast or slow, but they must be realtime.Programmability. Do DSPs need to be programmable? No:its quite feasible to process digital signals without a programmable architecture.In this article, however, DSP refers to programmable DSPmore specificallyto user-programmable DSPs, because my bias is that thats where the most interesting architectural issues lie. Often,the most demanding applications have required nonpro-grammable architectures. For instance,first-generation programmable DSPs could execute a single channel of the 32-Kbps ADPCM/DLQ,(adaptive differential pulse code modulation/dynamic locking quantizer) codec,whereas a special custom-integrated circuit that was not program-mable but deeply pipelined could run eight channels in the same technology.Thereason for this is that programmability comes at a cost Every single operation in a programmable chipno matter how simplerequires fetch-decode-execute. Thats a lot of silicon area and power devoted to,say,shifting left by two bits. Nonprogrammable architectures succeed when the shift-left-by-two-bits function is a small building block allowing other buildingblocks to operate simultaneously. Its easy to imagine many building blocks working simultaneously to achieve a 10x performance advantage in nonprogrammable logic.The problem with specialized DSP hardware is that you have to develop a new chip for each application. As development costs increase the break-even point is constantly shifting in favor of using a programmable architecture.More Power. Higher clock speed permits more instructions to be executed during a fixed time interval. In 1980,the Bell Labs team struggled to run DSP-1 at 5 MHz; today in 130-nm technology,clock speeds greater than 500 MHz can be attained. The advantage of more instructions in a fixed time period can be used to achieve one or more of the following.1.At a fixed data ratemore complicated algorithms can be programmed.2.At a fixed data rate, more channels of the same algo-rithm can be programmed.3.At a higher data rate,algorithms of similar complexity can be programmed.An example of the first case is G.729A,a CELP (coded-excited linear predictor) speech codec. It allows good quality at low data rates.The algorithm requires about 30 times more computations per sample than G.711 PCM. Examples of number 2 are VoIP (voice over IP) applica-tions where four channels are supported for SoHo (small office/home office) products and up to 256 or more channels for CO (central office) products. Channel den-sity is the key metric for VoIP processing. An example of the third case is the MPEG-2 video compression algorithm applied to decode DVDs at dif-ferent picture resolutions.The computational power is directly proportional to the videoresolution.Stretching MPEG-2 from NTSC (National Television System Commit-tee) resolution to high definition requires not only a six-fold increase in processing power but new blue laser DVD technology for faster readout of the data from the disk.In addition, advancing VLSI permits the program-mable architecture to reduce power and/or cost for a fixed algorithm at a fixed data rate.Advancing technology conspires in many ways to move the boundary in favor of programmable DSPs. Applications that require highly spe-cialized design today become programs for inexpensive DSPs tomorrow;costly power-hungry DSPs today become the jelly beans of tomorrow. The past 25 years has seen the ascendancy of the user-programmable DSP as the dominant architectural approach to implementing digital signal processing applications.DSP architecture is driven by a number of specialized application characteristics. Lets look at a few of these before returning to the architectureal influence of the all-important realtime constrain. The DSP program must sustain processing at the realtime rate under all circumstances.and.in fact the programmer mustsomehow know that this has been accomplished so that the application doesnt fail in the field. In other wordsthe DSP program must deterministically allocate realtime. Sources of indeterminacy common in desktop CPUs can be catastrophic for the DSP programmer. For example.page faults and cache misses can cause hundreds of cycles to be missed by the CPU as it is idled while the operation is satisfied.If you must sample a value every microsecond, then the page fault or cache miss could cause the window to be missed.As a result, DSPs need either fixed memories or caches that can be locked after the program is booted.Other less critical examples of indeterminacy include branch prediction and data-dependent termination of functions such as “divide” . Although nice for the average case, the DSP program must alsoallow for the worst case.Deterministic allocation of realtime not only must be achieved but tradition-ally DSPs have made it straightforward to achieve. In newer DSPs, realtime allocation is indeed know-able at compile time, but very careful profiling and iterative programming are often required to achieve the desired outcome. ILLUSTRATION: THE TI TMS320C54XXTo bring the discus-sion down to earth, lets illustrate with a real DSP. Targeted at the cellphone, TIs TMS320C54xx was introduced in 1994; in a sense, it is the fruition of TIs 16-bit DSP product line, which started with the introduction of the TMS32010 in 1983 and moved through the C1x, C2x, C2xx, and C5x generations to the C54xx. Although strict compat-ibility wasnt maintained, the follow-on architectures were close enough for TI to migrate its growing customer base with eachnew product generation much as Intel has done with the x86 family. Earlier TI DSPs sacrificed much performance to improve ease of use. Numerous other shortcomings such as the lack of accumulator guard bits were also rectified over the years. Table 1 shows how the TMS320C54xx has addressed each of the DSP features discussed here. For later comparison the TMS320C62xx is also listed. THE 16-BIT DSP RUNS OUT OF GASAnother form of “accumulation” other than the multiply-accumulate arithmetic operation was taking place in the TI DSP product line: by the mid-1990s, the TI architecture had grown to more than 130 instructions. New specialized instructions are one way of improv-ing performancethe way early DSPs used to meet cost goals. It became difficult to pack new instructions into theTMS320C54xxs burdened instruction set. Clock speed can be increased over time but does not take full advantage of advancing technology if the CISC instruc-tion growth continues. Somehow the DSP architecture needed to find a way to use the extra transistors of later-generation IC technology to increase performance. Deeper pipelining gives little benefit because the deeper pipeline must benefit all critical paths and CISC instruc-tions have many complex critical paths. An alternative strategy, VLIW (very long instruction word) parallelism, boosts performance by executing multiple instructions in parallel. VLIW is relatively ineffective on CISC instruction sets because its difficult to identify instructions that are commonly executed in parallel. It is also important to note that compilers have had little success with complex 16-bit DSP instruction sets.Yet as higher clock speeds and larger local memories per-mit larger programs, the demand for good DSP compilers becomes paramount. Consequently, the 16-bit DSP is out of gas: Its too complicated to scale performance with Moores law and too complicated to support good compi-lationWhile the C54xx was running 160 MHz using full custom 0.15m circuit design, the StrongARM RISC broke 600 MHz in 0.18m.Faced with this crisis, in 1997 TI introduced the all-new 32-bit VelociTI instruction set with its TMS320C62xx architecture. The TMS320C62xx has had enormous publicity as an eight-issue VLIW architecture (thus, the real instruction length is 8 x 32 or 256 bits, and it is pos-sible to execute eight 32-bit instructions in parallel on the chip). Less remarked, but equally important, is that each instruction is a relatively simple 32-bit RISC-like instruc-tion. In fact, its ironic that RISCs have included multiply-accumulate instructions since the mid-1990s, but TIthe company that has shipped more multiply-accumulates than any vendorchose to “out-RISC the RISCs” by requiring a multiply followed by an add instruction to implement the common DSP kernel.I call the new RISC-like DSP instruction sets,”RISC-DSP” . For an illustration of RISC-DSP. lets return to the FIR filter program. We saw that the instruction count of the inner loop is nine times better in the DSP case than for the conventional RISC.Keep in mind, though that clock speeds today are 100 times that of the 1980s when DSPs started down the CISC path. As a result.the RISC can execute the FIR almost 10 times faster than a 1980s DSP but one-tenth the speed of an optimized DSP architecture with the same clock speed-assuming of course that the in 1980 In 1980 the dial needed to be turned all the way to “DSP” in order to meet the minimal performance goals today the architect can choose different points on the spectrum with less performance. At todays clock speeds RISC-DSP perfor-mance will be sufficient for many applications and have other advantages as well.Sources and destinations from a general-purpose register file are easily encoded in a 32-bit RISC-DSP instruction making compilers more successful. Decoupling data loads from execution permits higher clock speed because data can be preloaded into a general-purpose register file. For each special feature, careful study of the potential number of instructions saved,critical path impact, interrupt overhead,and,of course, compila-tion is required.To summarize, 32-bit RISC-DSP instruction sets have moved DSPs onto the historic RISC technology learning curve.APPLICATIONS OF RISC + DSPWeve seen that the need for good tools and continued performance scaling have forced DSP architects to break with the complex 16-bit instruction sets of the past.RISC-DSP. However really comes to fruition in applications combining both “RISC tasks” and”DSP tasks” . Applica-tions of this type are proliferating commensurate with DSP applications on packet networks. An important example is the 3G wireless handset of the near future with video communications and speech recognition.Table 3 lists the key tasks classifying them aeither conventional RISC tasks or conventional DSP tasksWe see that a single RISC-DSP at about 200 MHz has suf-ficient performance for all tasks.9 The important advan-tage achievable in this application is that separate RISC and DSP chipsor separate RISC and DSP coresarent required. Significant architectural efficiency is gained because data doesnt need to be communicated between two differentsubsystems.This efficiency translates into hardware and performance advantages and therefore reduced cost and power. Because this is a handheld con-sumer device opportunities to save power and cost are critically important. The key barrier to merging DSP applications and RISCapplications on a common processor is the need for deterministic response time.The RISC processor often supports an operating system complicating the realtime problem. Packetized networks however, have relaxed the realtime constraint somewhat The samples arrive in packets; therefore,the realtime response rate is the (somewhat irregular) packet arrival rate. For example,80,000 packets per second are transmitted over 1 GigE (Gigabit Ethernet). MontaVistas sponsored Linux preemptive kernel guarantees a worst-case kernel preemption latencyunder 1 millisecond on several CPUs.VxWorks guaran-tees an interrupt response of a few microseconds on a 500-MHz Pentium.So DSP applications can often now be run under major real-time operating systems.The Siemens Tricore deserves recognition asone of the first RISC-DSPs:“Tri”signifies that microproces-sor DSP and microcontrol functions are combined in a common processor. Intel and Analog Devices have recently collaborated to build the Intel MSA (Micro Signal Architecture). The first produc,the ADSP-21535 (Blackfin) appears to be targeted at the 3G cellphone.StarCore and the Philips Trimedia are two additional high-perfor-mance RISC-DSP architectures each with VLIW imple-mentations.Coming from the RISC side,all vendors are taking digital signal processing requirements into account:ARM with “E” extensions Hitachi with SH-DSP now into its third generation IBMs PowerPC with Book E. MIPS has recently announced CoreExtend.Jonah Probell has demonstrated that DSP extensions with CoreExtend can achieve 3x speed-up on audio applications.10 INTO THE FUTUREVLIW architectures applied to RISC-DSP instruction sets offer an important path for increasing performance but the silicon cost of these architectures is not neg-ligible.Although the eight functional units in the TI TMS320C62xx data path have capability well beyond the C54xx when applied to a typical case like the direct-form FIR the eight-issue C62xx architecture uses 256 instruction bits to accomplish about what the C54xx can do in 16 bits. The extra silicon cost also extends to data-path elements and to the 15 ports on the register file required to sustain the eight functional units.As a result,TIs VelociTI products are positioned for high-perfor-manceapplications that,at the same time are not price-and power-sensitive.Another turn of the technology crank will be needed before VLIW architectures crowd out older 16-bit DSPs altogether.The H.264 codec is an example of an application requiring VLIW DSP.UB Video has developed H.264 decoder software for the 600-MHz TI TMS320DM642. This device uses the C64xx core along with specialized audio and video interfacing. It is capable of 4 800 MMACs (million multiply-accumulates per second) in eight-bit precision.The UB Video software supports decode at SDTV (standard-definition TV) resolutions.Itsimpor-tant for H.264 decoder ICs to support the vast number of MPEG-2-encoded DVDs,as well as other codecs and future evolution in the ITU-T/ISO standard itself The view of TIs Eric Braddom,worldwide manager for DSP video imaging that “programmability is essential at this stage,” is understandable from a technical as well as busi-ness perspective.11Meanwhile,there is still room for architecturalinno-vation within the framework of VLIW using RISC-DSP instruction sets,The promise of H.264 in the DVD market is its potential for high-definition (1080i,720p) decoding. Currently,HD resolution in H.264 is beyond the 600-MHz DM642.TI has announced it will apply its forthcoming 1-GHz DSP.Other high-end VLIW DSPs such as Philips Trimedia,with five-instruction-issue arent waiting and are expected to attack the HD problem soon.Other competi-tors will reduce programmability,resorting to specialized hardware for MPEG-2 and H.264 alone To see how far DSP architectures are from “matu-rity”its eye-opening to look at Appendix C“Survey of Architectures”in Hennessey and Pattersons text 12 The authors compare five RISC architectures.After a decade of research on compiler performance using well-established benchmarks,we find that RISCs are more alike than dif-ferent.DSPs are a long way from “Appendix Cstatus” but now that DSP applications are mainstream and both RISC vendors and DSP vendors are converging on RISC-DSP, the increasing cost of software developmentalong with the emergence of good benchmarks such as BDTI-mark2000 from Berkeley Design Technology (BDTI) and EEMBC (Embedded Microprocessor Benchmark Consor-tium) with which to measure design progresswill drive DSP architectures to become more similar, not unlike the path RISC followed a generation ago. Whenever a programmable .DSP architecture can meet an applications cost and power goals,it will be the pre-ferred solution. But what about the applications that just cant fit? In the desktop market. application and system software seem to lag VLSI capabilities;in digital signal processing,the demands of “”faster/cheaper/lower-power” have always pushed DSP VLSI. Nick Tredennick. believes that the “leading-edge wedge of zero-cost, zero-power, and zero-delay segments of the embedded systems mar-ket”will drive DSPs to dynamic logic design.中文翻译 DSP的发展 W. PATRICK HAYS 在线出版：2004年6月23日 施普林格科学+商业媒体b.v. 2004 摘要 现在的世界是以信息的传播、存储和处理为代表的数字时代。随着数字信号处理器DSP的发展工程师们能够相对容易执行复杂的算法。在我们周围汽车、数码相机、MP3和DVD播放器、调制解调器等等都应用了DSP。它们广泛地使用数字信号处理引发了的DSP架构巨大变化而这反过来又使工程师执行算法日益复杂。今天的DSP程序员必须精通中不仅数字信号处理而且计算机架构和软件工程。 关键词 DSP电机控制系统 英特尔2920包括芯片数字/模拟数字/模拟和A / D 模拟/ 数字转换器但缺乏一个硬件乘法器和很快从市场上消失。 NEC公司由于一个项目在NEC公司PD7720 一个最成功的DSP系列所有的时间。贝尔实验室的DSP - 1和NEC PD7720人上宣布ISSCC80 。基于DSP - 1取得5 - MHz的时钟速度快执行1.25 - MB的乘法累积每第二次在4个时钟周期每个-足以使触摸声调接收过滤器来执行实时。曾经强大的性能要求音频接收器现在滑稽容易但新应用又出现在过去20年把新的要求 DSP技术。据总裁Will Strauss先生和首席分析师 Forward Concepts公司在“数字信号处理器出货量增长了健康百分之二十四在2003年我们预测略高增长的2004年在25 百分之。长远来说我们预测百分之22.6 复合增长率到2007年。因此比赛以升压 DSP性能运行在可接受的算法成本开辟新的商业市场。它是也许太圆滑项目这一趋势将无限期未来。事实上精明的分析家们定期预测的消亡数字信号处理器。将性能要求超出可编程能力 DSP架构保持上涨从而一个新的要求办法或者如果是数字信号处理器保持其历史生长曲线什么样工具和架构的需要最终这些将回答问题的创造性建筑师3月市场竞争及应用的需求。的目标本文阐明当前和未来趋势的审查如何利用技术及应用压力形DSP架构在过去。首先重要的是要区分数字信号处理和数字信号处理器。那个技术和应用的数字信号处理法相对于模拟信号处理是很好建立和更为重要的商业比。曾经在整个文章指的是数字信号处理器的VLSI非常大规模集成处理器组成部分。因此有什么特殊要求的数字信号处理作出从另一个不同的DSP的可编程处理器基本应用DSP架构的特点是驾驶的要求实时信号处理。实时是指信号代表身体或“真正的”事件。数字信号处理器的设计实时信号处理因此必须能够进程样本他们的速度和产生到达。增加重大延误或延迟到输出可反感。而高利率常常实时DSP的要求被“快”快速实时是不同的概念。例如模拟集成电路的设计必须是快速的越快越好但并不适用如果失败模拟器完成慢一点。相反实时应用不必快速例如一所医院房间心脏监视器不需要快速30赫兹样本率但并不需要实时;这将是灾难性的如果处理的抽样调查了这么长时间经过几时监测显示是五分钟前的旧数据。并非所有的数字信号处理应用需要实时处理。许多应用程序执行离线。例如编码的高保真音频掌握的CD - ROM使用先进的数字信号亲处理算法但没有做的工作是在实时。因此DSP是不需要任何旧处理器速度不够快的工程师回家吃晚饭将这样做。总之最重要的区别DSP的技术特点是它们的过程实时信号该信号可以快或慢但它们必须实时。可编程。做DSP的需要可编程编号这是完全可行的处理数字信号不可编程架构。在这篇文章中然而数字信号处理器指可编程DSP 更具体地说对用户可编程DSP 因为我的偏见是这就是最有趣的建筑设计问题所在。通常最苛刻的应用要求可编程架构。例如第一代可编程DSP可以执行的单一渠道的32 - Kbps的编码/ DLQ 自适应差分脉冲编码调制/动态锁量化编解码器而特别定制集成电路这不是程序 mable但深感流水线可以运行8个通道相同的技术。这样做的理由是编程是在费用每一个行动一个可编程的芯片没有无论多么简单的要求取回解码执行。这是大量的硅芯片面积和功耗专门讨论也就是说转移留下的两个位。Nonprogrammable架构成功 ceed的转变时左对二位的功能是一个小积木积木允许其他经营同时。这很容易想象许多积木。工作同时进行以实现10倍性能优势nonprogrammable逻辑。存在的问题专门的DSP硬件是你必须发展一个新的芯片为每个应用程序。由于开发成本增加盈亏平衡点是不断变化的赞成采用可编程架构。更多的权力。提高了时钟速度允许更多的教学筹措期间被处决的固定时间间隔。1980年在贝尔实验室的团队挣扎运行的DSP - 1在5 MHz的今天在130纳米技术时钟速度大于500 兆赫才能实现。如下 1.在一个固定的数据速率更复杂的算法可以编程。 2.在一个固定的数据速率多渠道的同一算法算法可以编程。 3 .在更高的数据速率算法类似复杂可以编程。 一个例子第一个案件是G.729A的编码编码激励线性预测语音编解码器。它允许良好在低质量的数据传输速率。该算法需要大约30 倍计算每个样品超过条G.711的PCM 。实例数2 VoIP IP语音应用在四个渠道筹措支持为SOHO小型办公室/家庭办公室的产品多达256个或更多合作渠道办事处的产品。频道登大学是关键指标VoIP处理。一个例子第三起案件是MPEG - 2视频压缩算法用于解码DVD光盘上区分不一样图片决议。计算能力成正比视频分辨率。拉伸的MPEG - 2从NTSC系统国家电视系统承诺开球决议高清不仅需要6 倍的处理能力但在新的蓝色激光的DVD 技术的快速读取数据的磁盘。此外推进超大规模集成电路许可证的程序mable架构以降低功耗和/或费用定额算法在一个固定的数据速率。推进技术共谋在许多方面为推动边界赞成可编程DSP 。应用需要高度特异性 cialized设计方案今天成为廉价 DSP的明天;昂贵耗电DSP的今天已成为在糖豆明天。在过去25年里看到占支配地位的用户可编程DSP作为占主导地位的建筑方式来执行数字信号处理应用。DSP的程序必须维持在实时处理率在所有情况下并在事实上程序员必须以某种方式知道这已经完成使应用不失败领域。换言之DSP的程序必须分配实时。来源的不确定性共同在台式机处理器可能是灾难性的DSP的编程。例如页错误和缓存错过可以造成数百周期错过的CPU的因为它是闲置的而行动是满意的。如果您必须采样值每微秒那么页错误或缓存小姐可能会导致窗口错过。因此DSP的需要或者固定存储器或高速缓存可锁定程序后启动。其他不太重要的例子不确定性包括分支预测和数据依赖终止功能如“鸿沟”。虽然漂亮的平均情况下 DSP的程序也必须允许为最坏的情况分配实时不仅要得到实现但传统的盟友DSP的已直接实现。在新的数字信号处理器实时分配确实知道能够在编译的时候但非常认真分析和反复编程往往需要