基于单片机控制的智能应变仪设计【自动化毕业论文开题报告外文翻译说明书】.zip
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基于单片机控制的智能应变仪设计【自动化毕业论文开题报告外文翻译说明书】.zip,自动化毕业论文开题报告外文翻译说明书,毕业设计的开题报告
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毕 业 设 计（论 文）任 务 书1本毕业设计（论文）课题应达到的目的： 通过毕业设计，使学生受到自动化工程师所必备的综合训练，在不同程度上提高各种设计及应用能力，具体包括以下几方面：1. 调查研究、中外文献检索与阅读的能力。2. 综合运用专业理论、知识分析解决实际问题的能力。3. 定性与定量相结合的独立研究与论证的能力。4. 实验方案的制定、仪器设备的选用、调试及实验数据的测试、采集与分析处理的能力。5. 设计、计算与绘图的能力，包括使用计算机的能力。6. 逻辑思维与形象思维相结合的文字及口头表达的能力。2本毕业设计（论文）课题任务的内容和要求（包括原始数据、技术要求、工作要求等）： 1. 本课题要求设计一种以89C52单片机为控制核心的智能型电阻应变仪,它可以通过键盘操作实现对数据采集、显示和存储及通信等功能的人工智能控制。本系统包括89C52单片机及最小应用系统，前向A/D转换通道，人机对话系统和相互通道配置，单片机系统通过一个RS232/485转换器与PC机通信。系统上电后，主机89052进人监控状态，显示提示符，同时也完成对各扩展端口的初始化工作。按下数据采集功能键，系统进人相应的中断程序开始进行数据采集。被测量经测量电桥、模拟放大、A/D转换后，由单片机进行数据计算、处理，测量结果由LED数码管显示。 2.设计系统的硬件电路和软件程序，包括详细的硬件设备配置，系统连接，程序调试等详细步骤；3.最终完成一篇符合金陵科技学院毕业论文规范的系统技术文档，包括各类技术资料，电路图纸，程序等；4.系统要有实际的硬件展示，并能够通电运行；5.本子系统要与整个系统能够配合运行。毕 业 设 计（论 文）任 务 书3对本毕业设计（论文）课题成果的要求包括图表、实物等硬件要求： 1.按期完成一篇符合金陵科技学院论文规范的毕业设计说明书（毕业论文），能详细说明设计步骤和思路；2.能有结构完整，合理可靠的技术方案；3.能有相应的电气部分硬件电路设计说明；4.有相应的图纸和技术参数说明。5.要求调试成功，并在答辩时完成实际系统展示。4主要参考文献： 1. 王俊峰,孟令启.现代传感器应用技术M.北京:机械工业出版社,2007.2. 林震宇. 新型智能静态应变仪J.仪器仪表学报, 2005,(8).3. 钟立. 一种基于单片机控制的智能型应变仪设计J.自动化技术与应用2006,(3).4. 陈颖. 数字化多功能电阻应变仪J.自动化与仪表, 2002,(2).5. 何立民. 单片机高级教程(第1版)M北京：北京航空航天大学出版社，2001.6. 赵晓安. MCS-51单片机原理及应用M. 天津：天津大学出版社，2001.7. 李广第 单片机基础M北京：北京航空航天大学出版社，1999.8. 徐惠民，安德宁 单片微型计算机原理接口与应用M 北京：北京邮电大学出版社，1996。9. 金发庆.传感器技术与应用M.北京:机械工业出版社,2006.10. 夏继强. 单片机实验与实践教程M. 北京：北京航空航天大学出版社, 2001. 11. 孙洪程.过程控制工程设计(第2版)M.北京:化学工业出版社,2009.12. 魏克新.自动控制综合应用技术M.北京:机械工业出版社,2007.13. 白志刚.自动调节系统解析与PID整定M.北京:化学工业出版社,2012.14. 沈聿农.传感器及应用技术M.北京:化学工业出版社,2001.15. 范晶彦.传感器与检测技术应用M.北京:机械工业出版社,2005.毕 业 设 计（论 文）任 务 书5本毕业设计（论文）课题工作进度计划：2015.11.102015.12.13调研、收集相关资料、对学生进行初步辅导，拟题、选题、填写任务书。2015.12.152015.12.31学生查看任务书，为毕业设计的顺利完成，进行前期准备。12月31日前正式下发任务书。12月21日两个系提交专业选题分析总结（撰写要求详见对内通知中附件2）2016.01.092016.04.05学生在指导教师的具体指导下进行毕业设计创作；拟定论文提纲或设计说明书（下称文档）提纲；撰写及提交开题报告、外文参考资料及译文、论文大纲；在2016年4月5日前学生要提交基本完成的毕业设计创作成果以及文档的撰写提纲，作为中期检查的依据。指导教师指导、审阅，定稿由指导教师给出评语，对论文主要工作未通过的学生下发整改通知。2016.04.062016.04.10提交中期课题完成情况报告给指导教师审阅；各专业组织中期检查（含毕业设计成果验收检查）。2016.04.112016.05.10进行毕业设计文档撰写；2016年5月8日为学生毕业设计文档定稿截止日。2016年5月9日-13日，指导教师和评阅教师通过毕业设计（论文）管理系统对学生的毕业设计以及文档进行评阅，包括打分和评语。5月1日前，做好答辩安排，通知学生回校进行答辨2016.05.142016.05.15查看答辩安排，毕业设计（论文）小组答辩2016.05.162016.05.29对未通过答辨的学生进行二次答辨完成毕业设计的成绩录入2016.05.302016.06.07根据答辩情况修改毕业设计（论文）的相关材料，并在毕业设计（论文）管理系统中上传最终稿，并且上交纸质稿。2016年6月7日为学生毕业设计文档最终稿提交截止日。2016.06.072016.06.30各系提交本届毕业设计（论文）的工作书面总结及相关材料。所在专业审查意见：通过负责人： 2015 年 12 月21 日 毕 业 设 计（论文） 开 题 报 告 1结合毕业设计（论文）课题情况，根据所查阅的文献资料，每人撰写不少于1000字左右的文献综述： 随着科学技术和生产的发展,需要对各种参数进行测量。尤其是应变的测试,在航空航天、机械制造、工程建筑、交通运输、船舶及桥梁等研究中显得更为重要。目前,应变仪的种类很多,其灵敏度也较高,但其功能却较单一,价格昂贵、无法进行系统集成,在实际使用中很不方便。因此,将单片机控制技术应用于应变仪,设计出一种相对先进的、能准确采集样本数据并进行相应处理,具备显示和存储、通信功能的数字化多功能应变仪是非常具有实用价值的。本文介绍一种以89c52单片机为控制核心的智能型电阻应变仪,它可以通过键盘操作实现对数据采集、显示和存储及通信等功能的人工智能控制。文中分析了应变仪测量原理,着重阐述了基于单片机控制电路的硬件构成和主要软件设计思想。该应变仪具有智能化、体积小、操作方便和抗干扰能力强等特点。应变测量时,应变片的电阻变化十分微小,输出的电压为毫伏级,必须经过放大到毫伏以上,才能进行A/D变换处理。传统放大电路一般利用多圈电位器和阻容元件以及运放来完成,用电位器对放大倍数等系统参数进行调节,当调节到合适的数值后将其锁定。如果输入不同种类的传感器信号和标准信号,由于它们的最大量程相差甚大,必须采用多套放大器电路。本装置的核心元件为近年研制的内含快闪存储器的高档单片微控制器89C52,其片内快闪存储器的编程和擦除完全用电实现,数据不易丢失,可保存10年。程序存储于微控制器内部,不需外部扩展程序存储器,且有强大的加密功能,使大量的数据不必在CPU和外部扩展程序存储器之间来回交换,大大提高了控制装置的抗干扰能力,这一优点对变化缓慢的应变力装置来说是至关重要且最为宝贵的。89C52片内含256字节RAM,但无法满足大量数据采集、存储及与外设通信的需要,故须对89C52作数据存储扩展。在此设计中数据存储器采用美国近年制造的X25045P,它将看门狗定时器、集成电路监控和电子编程可擦除存储器三种功能容为一体,降低了成本,完成了断电数据保护,提高了软件系统的可靠性和控制装置的抗干扰能力。CPU主频采用12M晶振,其ALE端信号经CD4013分频后输给ICL7135作为转换频率。主程序的任务是对89C52的初始化,如设置堆栈,预置各定时器控制字,初始化显示缓冲区,设置标志位,清内存等;然后显示开机初始化状态,扫描键盘,根据按下键的功能转各自的功能操作。显示程序主要的功能,是把设置在RAM中显示缓冲器的内容在LED数码管上显示出来,然后进入键盘扫描程序。键盘扫描程序是先判断有无键按下,一旦发现有键按下,就按照键的功能,转到相应的键处理程序执行命令要求的操作。如果无键按下,再返回显示程序。功能键处理子程序是执行相应的键功能。有采集、显示、存储、清零、回放等子程序。1 赵茂泰主编.智能仪器原理及应用M.电子工业出版社，1999. 2 相志文.用V/F变换器完成低成本高分辨A/D转换时与单片机的接口技术J.电气自动化，19903 康华光电子技术基础模拟部分第4版，高等教育出版社，2006 4 刘军单片机原理与接口技术华东理工大学出版社，2006 5 赖寿宏微型计算机控制技术机械工业出版社，2009 6 孙育才MCS-51系列单片微型计算机及其应用第4版，东南大学出版社，2006 7 王庆Protel 99 SE&DXP电路设计教程电子工业出版社，2008 8 白志刚.自动调节系统解析与PID整定M.北京:化学工业出版社,2012. 9 霍罡,曹辉.可编程序控制器模拟量及PID算法应用案例M.北京:高等教育出版社,2008. 10 郁汉琦.电气控制与可编程序控制应用技术M.南京:东南大学出版社,2009. 11 孟立凡，蓝金辉传感器原理与应用北京：电子工业出版社，2007.8. 12 孙洪程.过程控制工程设计(第2版)M.北京:化学工业出版社,2009. 13 万福君主编.单片微机原理系统设计与应用Ml.合肥:中国科学技术大学出版社，2001. 14 原继萍,刘海亮.数字式PID控制算法研究J.航天控制,2010,(05). 15 魏克新.自动控制综合应用技术M.北京:机械工业出版社,2007. 16 张如一主编.应变电测与传感器M.北京:清华大学出版社，2002. 毕 业 设 计（论文） 开 题 报 告 2本课题要研究或解决的问题和拟采用的研究手段（途径）： 本系统关键的部分是单片机系统,主要包括89C52单片机及最小应用系统,前向A/D转换通道,人机对话系统(包括薄膜按键及显示器设计)和相互通道配置(即单片机应用系统和上位机进行通信、控制),单片机系统通过一个RS232/485转换器与PC机通信。系统上电后,主机89C52进入监控状态,显示提示符,同时也完成对各扩展端口的初始化工作。按下数据采集功能键,系统进入相应的中断程序开始进行数据采集。被测量经测量电桥、模拟放大、A/D转换后,由单片机进行数据计算、处理,测量结果由LED数码管显示。上位机需要数据时,通过串行口发出取数据命令,单片机则把当前最新数据传送给上位机。通过对键盘上其它功能键的操作,可调用其它程序进行相应的操作。 毕 业 设 计（论文） 开 题 报 告 指导教师意见：1对“文献综述”的评语：综述内容较为丰富，参考文献合理，概括了单片机控制的智能应变仪设计的相关背景、基础知识、历史发展等，同时还对本课题所研究的任务进行了一定的阐述，对本课题的研究有一定的指导意义。2对本课题的深度、广度及工作量的意见和对设计（论文）结果的预测：本课题研究的任务是对单片机控制的智能应变仪进行设计，技术相对成熟，深度中等，但是涉及到的知识面较广，例如传感器技术、单片机技术、电子元器件相关知识等，学生可以通过实例调研，查阅专业资料，进行系统调试，来实现最终的设计任务和结果，并对自己的专业应用能力是一个非常大的提高。3.是否同意开题： 同意 不同意 指导教师： 2016 年 03 月 30 日所在专业审查意见：同意 负责人： 2016 年 03 月 30 日Structure and function of the MCS-51 seriesStructure and function of the MCS-51 series one-chip computer is a name of a piece of one-chip computer series which Intel Company produces. This company introduced 8 top-grade one-chip computers of MCS-51 series in 1980 after introducing 8 one-chip computers of MCS-48 series in 1976. It belong to a lot of kinds this line of one-chip computer the chips have,such as 8051, 8031, 8751, 80C51BH, 80C31BH,etc., their basic composition, basic performance and instruction system are all the same. 8051 daily representatives- 51 serial one-chip computers . An one-chip computer system is made up of several following parts: ( 1) One microprocessor of 8 (CPU). ( 2) At slice data memory RAM (128B/256B),it use not depositting not can reading /data that write, such as result not middle of operation, final result and data wanted to show, etc. ( 3) Procedure memory ROM/EPROM (4KB/8KB ), is used to preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM within some one-chip computers, such as 8031 , 8032, 80C ,etc. ( 4) Four 8 run side by side I/O interface P0 four P3, each mouth can use as introduction , may use as exporting too. ( 5) Two timer / counter, each timer / counter may set up and count in the way, used to count to the external incident, can set up into a timing way too, and can according to count or result of timing realize the control of the computer. ( 6) Five cut off cutting off the control system of the source . ( 7) One all duplexing serial I/O mouth of UART (universal asynchronous receiver/transmitter (UART) ), is it realize one-chip computer or one-chip computer and serial communication of computer to use for. ( 8) Stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity need outer. Allow oscillation frequency as 12 megahertas now at most. Every the above-mentioned part was joined through the inside data bus .Among them, CPU is a core of the one-chip computer, it is the control of the computer and command centre, made up of such parts as arithmetic unit and controller , etc. The arithmetic unit can carry on 8 persons of arithmetic operation and unit ALU of logic operation while including one, the 1 storing device temporarilies of 8, storing device 2 temporarily, 8s accumulation device ACC, register B and procedure state register PSW, etc. Person who accumulate ACC count by 2 input ends entered of checking etc. temporarily as one operation often, come from person who store 1 operation is it is it make operation to go on to count temporarily , operation result and loopback ACC with another one. In addition, ACC is often regarded as the transfer station of data transmission on 8051 inside . The same as general microprocessor, it is the busiest register. Help remembering that agreeing with A expresses in the order. The controller includes the procedure counter , the order is depositted, the order decipher, the oscillator and timing circuit, etc. The procedure counter is made up of counter of 8 for two, amounts to 16. It is a byte address counter of the procedure in fact, the content is the next IA that will carried out in PC. The content which changes it can change the direction that the procedure carries out . Shake the circuit in 8051 one-chip computers, only need outer quartz crystal and frequency to finely tune the electric capacity, its frequency range is its 12MHZ of 1.2MHZ. This pulse signal, as 8051 basic beats of working, namely the minimum unit of time. 8051 is the same as other computers, the work in harmony under the control of the basic beat, just like an orchestra according to the beat play that is commanded. There are ROM (procedure memory , can only read ) and RAM in 8051 slices (data memory, can is it can write ) two to read, they have each independent memory address space, dispose way to be the same with general memory of computer. Procedure 8051 memory and 8751 slice procedure memory capacity 4KB, address begin from 0000H, used for preserving the procedure and form constant. Data 8051- 8751 8031 of memory data memory 128B, address false 00FH, use for middle result to deposit operation, the data are stored temporarily and the data are buffered etc. In RAM of this 128B, there is unit of 32 byteses that can be appointed as the job register, this and general microprocessor is different, 8051 slice RAM and job register rank one formation the same to arrange the location. It is not very the same that the memory of MCS-51 series one-chip computer and general computer disposes the way in addition. General computer for first address space, ROM and RAM can arrange in different space within the range of this address at will, namely the addresses of ROM and RAM, with distributing different address space in a formation. While visiting the memory, corresponding and only an address Memory unit, can ROM, it can be RAM too, and by visiting the order similarly. This kind of memory structure is called the structure of Princeton. 8051 memories are divided into procedure memory space and data memory space on the physics structure, there are four memory spaces in all: The procedure stores in one and data memory space outside data memory and one in procedure memory space and one outside one, the structure forms of this kind of procedure device and data memory separated form data memory, called Harvard structure. But use the angle from users, 8051 memory address space is divided into three kinds: (1) In the slice, arrange blocks of FFFFH , 0000H of location , in unison outside the slice (use 16 addresses). (2) The data memory address space outside one of 64KB, the address is arranged from 0000H 64KB FFFFH (with 16 addresses ) too to the location. (3) Data memory address space of 256B (use 8 addresses). Three above-mentioned memory space addresses overlap, for distinguishing and designing the order symbol of different data transmission in the instruction system of 8051: CPU visit slice, ROM order spend MOVC , visit block RAM order uses MOVX outside the slice, RAM order uses MOV to visit in slice. 8051 one-chip computer have four 8 walk abreast I/O port, call P0, P1, P2 and P3. Each port is 8 accurate two-way mouths, accounts for 32 pins altogether. Every one I/O line can be used as introduction and exported independently. Each port includes a latch (namely special function register ), one exports the driver and a introduction buffer . Make data can latch when outputting, data can buffer when making introduction , but four function of passway these self-same. Expand among the system of memory outside having slice, four port these may serve as accurate two-way mouth of I/O in common use. Expand among the system of memory outside having slice, P2 mouth see high 8 address off; P0 mouth is a two-way bus, send the introduction of 8 low addresses and data / export in timesharing The circuit of 8051 one-chip computers and four I/O ports is very ingenious in design. Familiar with I/O port logical circuit, not only help to use ports correctly and rationally, and will inspire to designing the peripheral logical circuit of one-chip computer to some extent. Load ability and interface of port have certain requirement, because output grade, P0 of mouth and P1 end output, P3 of mouth grade different at structure, so, the load ability and interface of its door demand to have nothing in common with each other. P0 mouth is different from other mouths, its output grade draws the resistance supremly. When using it as the mouth in common use to use, output grade is it leak circuit to turn on, is it is it urge NMOS draw the resistance on taking to be outer with it while inputting to go out to fail. When being used as introduction, should write 1 to a latch first. Every one with P0 mouth can drive 8 Model LS TTL load to export. P1 mouth is an accurate two-way mouth too, used as I/O in common use. Different from P0 mouth output of circuit its, draw load resistance link with power on inside have. In fact, the resistance is that two effects are in charge of FET and together: One FET is in charge of load, its resistance is regular. Another one can is it lead to work with close at two state, make its President resistance value change approximate 0 or group value heavy two situation very. When it is 0 that the resistance is approximate , can draw the pin to the high level fast ; When resistance value is very large, P1 mouth, in order to hinder the introduction state high. Output as P1 mouth high electricity at ordinary times, can is it draw electric current load to offer outwards, draw the resistance on neednt answer and thenning. Here when the port is used as introduction, must write into 1 to the corresponding latch first too, make FET end. Relatively about 20,000 ohms because of the load resistance in scene and because 40,000 ohms, will not exert an influence on the data that are input. The structure of P2 some mouth is similar to P0 mouth, there are MUX switches. Is it similar to mouth partly to urge, but mouth large a conversion controls some than P1. P3 mouth one multi-functional port, mouth getting many than P1 it have and 3 door and 4 buffer. Two part these, make her besides accurate two-way function with P1 mouth just, can also use the second function of every pin, and door 3 function one switch in fact, it determines to be to output data of latch to output second signal of function. Act as W =At 1 oclock, output Q end signal; Act as Q =At 1 oclock, can output W line signal . At the time of programming, it is that the first function is still the second function but neednt have software that set up P3 mouth in advance . It hardware not inside is the automatic to have two function outputted when CPU carries on SFR and seeks the location (the location or the byte ) to visit to P3 mouth /at not lasting lining, there are inside hardware latch Qs =1.The operation principle of P3 mouth is similar to P1 mouth. Output grade , P3 of mouth , P1 of P1 , connect with inside have load resistance of drawing , every one of they can drive 4 Model LS TTL load to output. As while inputting the mouth, any TTL or NMOS circuit can drive P1 of 8051 one-chip computers as P3 mouth in a normal way . Because draw resistance on output grade of them have, can open a way collector too or drain-source resistance is it urge to open a way, do not need to have the resistance of drawing outerly . Mouths are all accurate two-way mouths too. When the conduct is input, must write the corresponding port latch with 1 first . As to 80C51 one-chip computer, port can only offer milliampere of output electric currents, is it output mouth go when urging one ordinary basing of transistor to regard as, should contact a resistance among the port and transistor base , in order to the electricity while restraining the high level from exporting P1P3 Being restored to the throne is the operation of initializing of an one-chip computer. Its main function is to turn PC into 0000H initially , make the one-chip computer begin to hold the conduct procedure from unit 0000H. Except that the ones that enter the system are initialized normally,as because procedure operate it make mistakes or operate there arent mistake, in order to extricate oneself from a predicament , need to be pressed and restored to the throne the key restarting too. It is an input end which is restored to the throne the signal in 8051 China RST pin. Restore to the throne signal high level effective , should sustain 24 shake cycle (namely 2 machine cycles ) the above its effective times. If 6 of frequency of utilization brilliant to shake, restore to the throne signal duration should exceed 4 delicate to finish restoring to the throne and operating. Produce the logic picture of circuit which is restored to the throne the signal:Restore to the throne the circuit and include two parts outside in the chip entirely. Outside that circuit produce to restore to the throne signal (RST ) hand over to Schmitts trigger, restore to the throne circuit sample to output , Schmitt of trigger constantly in each S5P2 , machine of cycle in having one more , then just got and restored to the throne and operated the necessary signal insidly. Restore to the throne resistance of circuit generally, electric capacity parameter suitable for 6 brilliant to shake, can is it restore to the throne signal high level duration greater than 2 machine cycles to guarantee. Being restored to the throne in the circuit is simple, its function is very important. Pieces of one-chip computer system could normal running,should first check it can restore to the throne not succeeding. Checking and can pop ones head and monitor the pin with the oscillograph tentatively, push and is restored to the throne the key, the wave form that observes and has enough range is exported (instantaneous), can also through is it restore to the throne circuit group holding value carry on the experiment to change.译文：MCS -51系列单片机的功能和结构MCS - 51系列单片机具有一个单芯片电脑的结构和功能，它是英特尔公司生产的系列产品的名称。这家公司在1976年推出后，引进8位单芯片的MCS - 48系列计算机后于1980年推出的8位的MCS - 51系列单芯片计算机。诸如此类的单芯片电脑有很多种，如8051，8031，8751，80C51BH，80C31BH等，其基本组成，基本性能和指令系统都是相同的。 8051是51系列单芯片电脑的代表。 一个单芯片的计算机系统由以下几个部分组成：（1）一个8位的微处理器（CPU）。（2）片内数据存储器RAM（128B/256B），它只读/写数据，如结果不在操作过程中，最终结果要显示数据（3）程序存储器ROM/ EPROM（4KB/8KB），是用来保存程序，一些初步的数据和切片的形式。但一些单芯片电脑没有考虑ROM / EPROM，如8031，8032，80C51等等。（4）4个8路运行的I / O接口，P0，P1,P2,P3，每口可以用作入口，也可以用作出口。 （5）两个定时/计数器，每个定时/计数器可设置和计数的方式，用来计数外部事件，可以设置成定时方式也可以根据计算结果或定时控制实现计算机。 （6）5个中断 （7）一个全双工串行的I / UART（通用异步接收器I口/发送器（UART），它是实现单芯片电脑或单芯片计算机和计算机的串行通信使用。 （8）振荡器和时钟产生电路，需要考虑石英晶体微调能力。允许振荡频率为12MHz，每一个上述的部分都是通过内部数据总线连接。其中CPU是一个芯片计算机的核心，它是计算机的指挥中心，是由算术单元和控制器等部分组成。算术单元可以进行8位算术运算和逻辑运算， ALU单元是其中一种运算器，1 8个存储设备，暂存设备的积累设备进行协调，程序状态寄存器PSW积累了2个输入端的计数等检查暂时作为一个操作往往由人来操作谁储存1输入的是它使操作去上暂时计数，另有一个操作的结果，回环协调。此外，协调往往是作为对8051内的数据传输转运站考虑。作为一般的微处理器，它是最繁忙的，帮助记住和同意与其的顺序表示。该控制器包括程序计数器，解密的顺序。振荡器和定时电路等的程序计数器是一个由8个计数器为2，总计 16位。这是一个字节的地址，其实程序计数器，是将在个人电脑内进行。从而改变它的内容可以改变方向的程序进行。在8051的单芯片电脑中的电路，只需要外部石英晶体和频率微调电容，其频率范围为1.2MHz的其12MHz的。这种脉冲信号，作为8051的工作，即单位时间的最低基本节奏。 8051是其他电脑一样，在拍控制的基本工作在和谐，就像一个管弦乐队，根据击败发挥是指挥。 有光盘（程序存储器，只能读取），并在8051片（数据存储器RAM，可以是可写可读，他们各自独立的内存地址空间，处理办法是，与一般的电脑记忆体相同。 8051和8751的程序存储器的存储容量4KB的程序切片，地址开始从0000H开始执行，维护的程序和形式不断使用。数据8051 - 8751的内存数据存储器128B条8031，地址虚假00FH，中层结果存入操作使用，数据存储和数据是暂时缓冲等。在这128B条内存，有32 字节，可以作为工作寄存器使用，这和一般的微处理器是不同的，8051片RAM和登记形成的同一级到安排的位置。这不是很相同的，MCS - 51系列内存的单芯片计算机和通用计算机作主除了道路。通用计算机的第一个地址空间，ROM和RAM，可安排在不同的空间在这个范围内的地址范围，即ROM和RAM地址的形成与分布在不同的地址空间。在访问内存，相应的，只有一个地址的内存单元，可以用外部存储，也可以内存，并通过访问顺序与此类似。这种内存结构的一种被称为普林斯顿结构。 8051记忆分为程序存储器空间和数据
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