EDA课后答案适用于朱正伟《EDA技术及应用》.doc

1 1.1、设计集成计数器 74161，设计要求如下： 4-BIT BINARY UP COUNTER WITH SYNCHRONOUS LOAD AND ASYNCHRONOUS CLEAR NOTE INPUTS： CLKLDNCLRNDCBA OUTPUTS：QD QC QB QA RCO *RCO = QD USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT4 IS PORT( CLK,LDN,CLRN : IN STD_LOGIC; D,C,B,A : IN STD_LOGIC; CARRY : OUT STD_LOGIC; QD,QC,QB,QA : OUT STD_LOGIC ); END; ARCHITECTURE A OF CNT4 IS SIGNAL DATA_IN: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN DATA_IN0); ELSIF CLKEVENT AND CLK=1 THEN IF LDN=0 THEN CNT:=DATA_IN; ELSE CNT:=CNT+1; END IF; END IF; CASE CNT IS WHEN 1111= CARRY CARRY=0; END CASE; QA=CNT(0); QB=CNT(1); QC=CNT(2); QD=CNT(3); END PROCESS; END A; 1.2、设计一个通用双向数据缓冲器，要求缓冲器的输入和输出端口 的位数可以由参数决定。 设计要求：N BIT 数据输入端口 A，B。工作使能端口 EN=0 时 2 双向总线缓冲器选通， DIR=1，则 A=B；反之 B=A。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY BIDIR IS GENERIC(N:INTEGER:=8); PORT(A,B :INOUT STD_LOGIC_VECTOR(N-1 DOWNTO 0); EN,DIR:IN STD_LOGIC); END; ARCHITECTURE A OF BIDIR IS BEGIN PROCESS(EN,DIR) BEGIN IF EN=0 THEN AZ); BZ); ELSE IF DIR=1 THEN B=A; ELSE A=B; END IF; END IF; END PROCESS; END A; 2.1、用 VHDL 语言编程实现十进制计数器，要求该计数器具有异步 复位、同步预置功能。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY CNT_10_2 IS PORT( CLK,CLR : IN STD_LOGIC; COUNT : OUT STD_LOGIC ); END; ARCHITECTURE A OF CNT_10_2 IS SIGNAL CNT_10 : INTEGER RANGE 0 TO 10; BEGIN PROCESS(CLK,CLR) BEGIN IF CLR=1 THEN CNT_10=0; ELSIF CLKEVENT AND CLK=1 THEN CNT_10=CNT_10+1; IF CNT_10=9 THEN CNT_10=0; COUNT=1; ELSE 3 COUNT=0; END IF; END IF; END PROCESS; END A; 2.2、设计实现一位全减器。 行为描述行为描述: : F_SUB4F_SUB4 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY F_SUB4 IS PORT( A,B,CIN : IN STD_LOGIC; DIFF,COUT : OUT STD_LOGIC ); END; ARCHITECTURE A OF F_SUB4 IS BEGIN DIFF=A XOR B XOR CIN; COUT=(NOT A AND B) OR (NOT A AND CIN) OR (B AND CIN); END A; 数据流描述数据流描述 F_SUB1F_SUB1 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY F_SUB1 IS PORT( A,B :IN STD_LOGIC; CIN :IN STD_LOGIC; DIFF,COUT : OUT STD_LOGIC ); END; ARCHITECTURE A OF F_SUB1 IS SIGNAL S :STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN S DIFF=0;COUT DIFF=1;COUT DIFF=1;COUT DIFF=0;COUT DIFF=1;COUT DIFF=0;COUT DIFF=0;COUT DIFF=1;COUT DIFF=X;COUT=X; END CASE; END PROCESS; END A; 数据流描述数据流描述F_SUB2 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY F_SUB2 IS PORT( A,B,CIN : IN STD_LOGIC; DIFF,COUT : OUT STD_LOGIC ); END; ARCHITECTURE A OF F_SUB2 IS SIGNAL S :STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL C :STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN S=CIN DIFF=C(1); COUT=C(0); C=00 WHEN S=000 ELSE 11 WHEN S=001 ELSE 10 WHEN S=010 ELSE 00 WHEN S=011 ELSE 11 WHEN S=100 ELSE 01 WHEN S=101 ELSE 00 WHEN S=110 ELSE 11 ; END A; 数据流描述数据流描述 F_SUB3F_SUB3 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY F_SUB3 IS PORT( A,B,CIN : IN STD_LOGIC; DIFF,COUT : OUT STD_LOGIC ); END; ARCHITECTURE A OF F_SUB3 IS SIGNAL S :STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL C :STD_LOGIC_VECTOR(1 DOWNTO 0); 5 BEGIN S=CIN DIFF=C(1); COUT=C(0); WITH S SELECT C=00 WHEN 000, 11 WHEN 001, 10 WHEN 010, 00 WHEN 011, 11 WHEN 100, 01 WHEN 101, 00 WHEN 110, 11 WHEN OTHERS; END A; 3.1、阅读教材 P181 页，例5-55并回答下列问题： （1） 、该程序的功能是什么？ （2） 、请写出该程序所有端口的功能描述。 3.2、试描述一个十进制BCD 码编码器，输出使能为低电平有效。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY BIN_BCD IS PORT( BIN : IN INTEGER RANGE 0 TO 20; -ENA : IN STD_LOGIC; BCD_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END; ARCHITECTURE A OF BIN_BCD IS BEGIN BINARY_BCD : BLOCK BEGIN BCD_OUT =00000000 WHEN BIN = 0 ELSE 00000001 WHEN BIN = 1 ELSE 00000010 WHEN BIN = 2 ELSE 00000011 WHEN BIN = 3 ELSE 00000100 WHEN BIN = 4 ELSE 00000101 WHEN BIN = 5 ELSE 00000110 WHEN BIN = 6 ELSE 00000111 WHEN BIN = 7 ELSE 00001000 WHEN BIN = 8 ELSE 00001001 WHEN BIN = 9 ELSE 00010000 WHEN BIN = 10 ELSE 00010001 WHEN BIN = 11 ELSE 00010010 WHEN BIN = 12 ELSE 00010011 WHEN BIN = 13 ELSE 00010100 WHEN BIN = 14 ELSE 6 00010101 WHEN BIN = 15 ELSE 00010110 WHEN BIN = 16 ELSE 00010111 WHEN BIN = 17 ELSE 00011000 WHEN BIN = 18 ELSE 00011001 WHEN BIN = 19 ELSE 00100000 WHEN BIN = 20 ELSE 00000000; END BLOCK; END A; 4.1、读教材 P151 页，例5-32的程序，并回答以下问题： （1）请画出该程序所描述的电路结构图，要求标清楚每一个端口以 及内部信号。 （串入/串出移位寄存器） 4.2、用 VHDL 语言设计一个能够实现任意整数进制的计数器。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; -* ENTITY FREQDV_N IS GENERIC(N:INTEGER:=6); PORT( CLK :IN STD_LOGIC; CLK_DIV : OUT STD_LOGIC ); END; ARCHITECTURE A OF FREQDV_N IS SIGNAL CNT : INTEGER RANGE 0 TO N; BEGIN PROCESS(CLK) BEGIN IF RISING_EDGE(CLK) THEN IF CNT=0 THEN CNT=N-1; CLK_DIV=1; ELSE CLK_DIV=0; CNT=CNT-1; END IF; END IF; END PROCESS; 7 END A; 5.1、设计一个序列信号发生器，要求能够循环输出序列 “01101001” 。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY RS_1 IS PORT( CP,S,R : IN STD_LOGIC; Q,NQ : OUT STD_LOGIC ); END; ARCHITECTURE A OF RS_1 IS SIGNAL S1,R1,Q1,NQ1:STD_LOGIC; BEGIN S1=S NAND CP; R1=R NAND CP; Q1=S1 NAND NQ1; NQ1=R1 NAND Q1; Q=Q1; NQ=NQ1; END A; 5.2、设计一个带复位端、置位端、CP 下降沿触发的 JK 触发器。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY JKFF IS PORT( J,K,RST,CLR : IN BIT; CLK : IN BIT; Q,NQ : OUT BIT ); END; ARCHITECTURE A OF JKFF IS SIGNAL Q_S,NQ_S : BIT; BEGIN PROCESS(J,K,RST,CLR,CLK) BEGIN IF RST=1 THEN Q_S=1; NQ_S=0; ELSIF CLKEVENT AND CLK=0 THEN IF CLR=1 THEN Q_S=0; NQ_S=1; ELSIF J=0 AND K=1 THEN Q_S=0; 8 NQ_S=1; ELSIF J=1 AND K=0 THEN Q_S=1; NQ_S=0; ELSIF J=1 AND K=1 THEN Q_S=NOT Q_S; NQ_S=NOT NQ_S; END IF; ELSE NULL; END IF; Q=Q_S; NQ=NQ_S; END PROCESS; END A; 6.1、用 VHDL 语句描述一个三态输出的双 4 选一的数据选择器，其 地址信号共用，且各有一个低电平有效的使能端。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY DUAL_MUX_41 IS PORT( A,B,C,D : IN STD_LOGIC; ENA_N,ENB_N : IN STD_LOGIC; S : IN STD_LOGIC_VECTOR(1 DOWNTO 0); OUTA,OUTB : OUT STD_LOGIC ); END; ARCHITECTURE A OF DUAL_MUX_41 IS SIGNAL P,Q : STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN P=ENA_N Q=ENB_N WITH P SELECT OUTA=A WHEN 000, B WHEN 001, C WHEN 010, D WHEN 011, Z WHEN OTHERS; WITH Q SELECT OUTB=A WHEN 000, B WHEN 001, C WHEN 010, D WHEN 011, Z WHEN OTHERS; END A; 6.2、用并行信号赋值语句实现 38 译码器。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; 9 ENTITY DECODER38 IS PORT(A,B,C,G1,G1A,A2B:IN STD_LOGIC; Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); END DECODER38; ARCHITECTURE BEHAVE38 OF DECODER38 IS SIGNAL INDA: STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN INDAQQQQQQQQQ=XXXXXXXX; END CASE; ELSE Q=11111111; END IF; END PROCESS; END BEHAVE38; 7.1、用并行信号赋值语句实现 8 选一数据选择器，要求有工作使能 端。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY MUX8 IS PORT(D0,D1,D2,D3,D4,D5,D6,D7:IN STD_LOGIC_VECTOR(7 DOWNTO 0); S0,S1,S2:IN STD_LOGIC; Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); END MUX8; ARCHITECTURE BEHAVE OF MUX8 IS SIGNAL S: STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN S =S2 WITH S SECLECT D =D0 WHEN 000, D1 WHEN 001, D2 WHEN 010, D3 WHEN 011, D4 WHEN 100, D5 WHEN 101, 10 D6 WHEN 110, D7 WHEN 111, XWHEN OTHERS; END BEHAVE; 7.2、用 VHDL 语言设计实现输出占空比为 50%的 1000 分频器。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY DIV_1000 IS PORT( CLK ,CLR: IN STD_LOGIC; DIV : OUT STD_LOGIC ); END; ARCHITECTURE A OF DIV_1000 IS SIGNAL Q : STD_LOGIC; BEGIN DIV=Q; PROCESS(CLK,CLR) VARIABLE CNT : INTEGER RANGE 0 TO 499; BEGIN IF CLR=1 THEN CNT:=0; Q=0; ELSIF RISING_EDGE(CLK) THEN IF CNT=499 THEN CNT:=0; Q=NOT Q; ELSE CNT:=CNT+1; END IF; END IF; END PROCESS; END A; 8.1、设计一个一位全减器。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY F_SUB3 IS PORT( A,B,CIN : IN STD_LOGIC; DIFF,COUT : OUT STD_LOGIC ); END; ARCHITECTURE A OF F_SUB3 IS SIGNAL S :STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL C :STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN 11 S=CIN DIFF=C(1); COUT=C(0); WITH S SELECT C=00 WHEN 000, 11 WHEN 001, 10 WHEN 010, 00 WHEN 011, 11 WHEN 100, 01 WHEN 101, 00 WHEN 110, 11 WHEN OTHERS; END A; 8.2、用元件例化语句描述一个四位的全减器。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY F_SUB4_1 IS PORT( A,B : IN STD_LOGIC_VECTOR(3 DOWNTO 0); CIN : IN STD_LOGIC; DIFF: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT: OUT STD_LOGIC ); END; ARCHITECTURE A OF F_SUB4_1 IS COMPONENT F_SUB1 IS PORT( A,B,CIN : IN STD_LOGIC; DIFF,COUT : OUT STD_LOGIC ); END COMPONENT; SIGNAL C :STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN U1: F_SUB1 PORT MAP(A(0),B(0),CIN,DIFF(0),C(0); U2: F_SUB1 PORT MAP(A(1),B(1),C(0),DIFF(1),C(1); U3: F_SUB1 PORT MAP(A(2),B(2),C(1),DIFF(2),C(2); U4: F_SUB1 PORT MAP(A(3),B(3),C(2),DIFF(3),C(3); COUT=C(3); END A; 9.1、利用生成语句描述一个由 N 个一位全减器构成的 N 位减法器， N 的默认值为 4。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY F_SUB4_2 IS 12 GENERIC (N : INTEGER := 4); PORT( A,B : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0); CIN : IN STD_LOGIC; DIFF: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0); COUT: OUT STD_LOGIC ); END; ARCHITECTURE A OF F_SUB4_2 IS COMPONENT F_SUB1 IS PORT( A,B,CIN : IN STD_LOGIC; DIFF,COUT : OUT STD_LOGIC ); END COMPONENT; SIGNAL C :STD_LOGIC_VECTOR(N DOWNTO 0); BEGIN C(0)=CIN; N1: FOR I IN 0 TO N-1 GENERATE U1: F_SUB1 PORT MAP(A(I),B(I),C(I),DIFF(I),C(I+1); END GENERATE; COUT=C(N); END A; 9.2、设计一个模为 60、具有异步复位、同步置数功能的 8421 码计 数器。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COUNT_60 IS PORT( CLK ,CLR,PST: IN STD_LOGIC; A : IN STD_LOGIC_VECTOR(5 DOWNTO 0); Q : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); CO: OUT STD_LOGIC ); END; ARCHITECTURE A OF COUNT_60 IS SIGNAL CNT: STD_LOGIC_VECTOR(5 DOWNTO 0); BEGIN Q=CNT; PROCESS(CLK,CLR,PST,A) BEGIN IF CLR=1 THEN CNT0); CO=0; ELSIF RISING_EDGE(CLK) THEN IF PST=1 THEN CNT=A; 13 ELSIF CNT=59 THEN CNT0); CO=1; ELSE CNT10) PORT MAP(A=TRIGGER_IN,CLK=CLK,Y=MONO_OUT); END A; 10.2、设计实现一个 83 优先编码器。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY MONO_TRIGGER IS -非可重复触发单稳态触发器 GENERIC(N:INTEGER:=5; -单稳态定时参数 M:INTEGER:=10); -定义定时参数取值范围 PORT( A,CLK: IN STD_LOGIC; Y : OUT STD_LOGIC ); END; 14 ARCHITECTURE A OF MONO_TRIGGER IS TYPE STATE IS(ST0,ST1,ST2); SIGNAL CURRENT_STATE,NEXT_STATE : STATE; SIGNAL Q:STD_LOGIC; BEGIN REG:PROCESS(A,CLK) BEGIN IF CLKEVENT AND CLK=1 THEN CURRENT_STATE IF A=0 THEN NEXT_STATE=ST0; Y=0; ELSE NEXT_STATE IF Q=1 THEN NEXT_STATE=ST2; Y=0; ELSE NEXT_STATE=ST1; Y IF A=1 THEN NEXT_STATE=ST2; Y=0; ELSE NEXT_STATE=ST0; Y NEXT_STATE=ST0; END CASE; END PROCESS; AUX_COUNT:PROCESS(CURRENT_STATE,CLK) VARIABLE COUNT : INTEGER RANGE 0 TO M; BEGIN IF CLKEVENT AND CLK=1 THEN IF CURRENT_STATE/=ST1 THEN COUNT:=N; ELSE COUNT:=COUNT-1; END IF; END IF; 15 IF COUNT=0 THEN Q=1; ELSE Q=0; END IF; END PROCESS; END A; 10-19 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY CODE_PAN IS PORT( X,RST,CLK : IN STD_LOGIC; Y : OUT STD_LOGIC ); END; ARCHITECTURE A OF CODE_PAN IS SIGNAL Q :STD_LOGIC_VECTOR(6 DOWNTO 0); BEGIN PROCESS(CLK,X,RST) BEGIN IF RST=1 THEN Q0); ELSIF CLKEVENT AND CLK=1 THEN Q(0)=X; Q(1)=Q(0); Q(2)=Q(1); Q(3)=Q(2); Q(4)=Q(3); Q(5)=Q(4); Q(6)=Q(5); END IF; END PROCESS; WITH Q SELECT Y=1 WHEN 1110010, 0 WHEN OTHERS; END A; 8-3 优先编码器(when-else 实现)： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY CODER IS PORE( D:IN STD_LOGIC_VECTOR(7 DOWNTO 0); OUTPUT:OUT STD_LOGIC_VECTOR(2 DOWNTO 0) ); END CODER; 16 ARCHITECTURE ART1 IS BEGIN OUTPUT=4 时，表示表决通过， 当 TEMPOUTPUTOUTPUT=1; END CASE ; END PROCESS; END BEHAVE; 4-7 给出 1 位全减器的 VHDL 描述,要求:首先设计 1 位半减器,然后 用例化语句将它们连接起来。设 X 为被减数，Y 为减数，DIFF 是输 出差(DIFF=X-Y),SUB_OUT 是借位输出(SUB_OUT=1,XY),SUB_IN 是借 位输入。 (1.1)：实现 1 位半减器 H_SUBER(DIFF=X-Y；S_OUT=1,XY) LIBRARY IEEE; -半减器描述(1):布尔方程描述方法 USE IEEE.STD_LOGIC_1164.ALL; ENTITY H_SUBER IS PORT( X,Y: IN STD_LOGIC; DIFF,S_OUT: OUT STD_LOGIC); END ENTITY H_SUBER; ARCHITECTURE HS1 OF H_SUBER IS 18 BEGIN DIFF YIN, DIFF=A, S_OUT=B); U2:H_SUBER PORT MAP(X=A, Y=SUB_IN, DIFF=DIFF_OUT,S_OUT=C); SUB_OUT = C OR B; END ARCHITECTURE FS1; 二进制全加器，元件声明与元件例化（二进制全加器，元件声明与元件例化（COMPONENT,PORTCOMPONENT,PORT MAPMAP） /或门 LIBRARY IEEE; ； USE IEEE.STD_LOGIC_1164.ALL; ENTITY OR2A IS PORT(A,B : IN STD_LOGIC; C : OUT STD_LOGIC); END OR2A; ARCHITECTURE ART1 OF OR2A IS BEGIN C=A OR B; END ART1; /半加器； LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY H_ADDER IS PORT(A,B : IN STD_LOGIC; CO,SO: OUT STD_LOGIC); END H_ADDER; 19 ARCHITECTURE ART2 OF H_ADDER IS BEGIN SO CIN,CO=F,SO=SUM); U3:OR2A PORT MAP(D,F,COUT); END ART3; 10 进制异步复位计数器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY CNT_10_2 IS PORT( CLK,CLR : IN STD_LOGIC; COUNT : OUT STD_LOGIC ); END; ARCHITECTURE A OF CNT_10_2 IS SIGNAL CNT_10 : INTEGER RANGE 0 TO 10; BEGIN PROCESS(CLK,CLR) BEGIN IF CLR=1 THEN CNT_10=0; ELSIF CLKEVENT AND CLK=1 THEN 20 CNT_10=CNT_10+1; IF CNT_10=9 THEN CNT_10=0; COUNT=1; ELSE COUNT=0; END IF; END IF; END PROCESS; END A; 10 进制异步复位可调占空比 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY CNT_10_1 IS PORT( CLK,CLR : IN STD_LOGIC; COUNT : OUT STD_LOGIC ); END; ARCHITECTURE A OF CNT_10_1 IS BEGIN PROCESS(CLK,CLR) VARIABLE CNT_10 : INTEGER RANGE 0 TO 10; BEGIN IF CLR=1 THEN CNT_10:=0; ELSIF CLKEVENT AND CLK=1 THEN CNT_10:=CNT_10+1; IF CNT_10=10 THEN CNT_10:=0; COUNT=1; ELSE COUNT=0; END IF; END IF; END PROCESS; END A; 10 进制同步复位计数器（用信号） LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY CNT_10_2 IS PORT( A : IN INTEGER RANGE 0 TO 10; CLK,CLR,PST : IN STD_LOGIC; COUNT : OUT STD_LOGIC ); END; 21 ARCHITECTURE A OF CNT_10_2 IS SIGNAL CNT_10: INTEGER RANGE 0 TO 9; BEGIN PROCESS(CLK,CLR,PST) -VARIABLE CNT_10 : INTEGER RANGE 0 TO 9; BEGIN IF CLR=1 THEN CNT_10=0; ELSIF CLKEVENT AND CLK=1 THEN IF PST=1 THEN CNT_10=A; ELSIF CNT_10=9 THEN CNT_10=0; COUNT=1; ELSE COUNT=0; CNT_10=CNT_10+1; END IF; END IF; END PROCESS; END A; N 位全减器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY F_SUB4_2 IS GENERIC (N : INTEGER := 4); PORT( A,B : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0); CIN : IN STD_LOGIC; DIFF: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0); COUT: OUT STD_LOGIC ); END; ARCHITECTURE A OF F_SUB4_2 IS COMPONENT F_SUB1 IS PORT( A,B,CIN : IN STD_LOGIC; DIFF,COUT : OUT STD_LOGIC ); END COMPONENT; SIGNAL C :STD_LOGIC_VECTOR(N DOWNTO 0); BEGIN C(0)=CIN; N1: FOR I IN 0 TO N-1 GENERATE U1: F_SUB1 PORT MAP(A(I),B(I),C(I),DIFF(I),C(I+1); END GENERATE; COUT=C(N); 22 END A; 带异步复位的能自启动的 4 位 l 环形计数器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY HUANXINGJISHU IS PORT(CLK,RS:IN STD_LOGIC; COUNTOUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END HUANXINGJISHU; ARCHITECTURE BEHAVE OF HUANXINGJISHU IS SIGNAL Q:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(RS,CLK) BEGIN IF RS=0 THEN QQQQQQQQQQQQQQQQQQ=0000; END CASE; END IF; END PROCESS