PWM信号发生器的设计程序(veriloghdl).doc

PWM信号发生器的设计程序module pwmgen(clk,rst,ce,addr,write,wrdata,read,bytesel,rddata,pwm);input clk,rst,ce;input 1:0addr;input write,read;input31:0wrdata;output31:0rddata;input31:0bytesel;output pwm;reg31:0clk_div_reg,duty_cycle_reg;reg control_reg;reg clk_div_reg_sel,duty_cycle_reg_sel,control_reg_sel;reg31:0pwm_cnt,rddata;reg pwm;wire pwm_ena;always(addr)beginclk_div_reg_sel=0;duty_cycle_reg_sel=0;control_reg_sel=0;case(addr)2b00:clk_div_reg_sel=1;2b01:duty_cycle_reg_sel=1;2b10:control_reg_sel=1;default:beginclk_div_reg_sel=0;duty_cycle_reg_sel=0;control_reg_sel=0;endendcaseendalways(posedge clk or negedge rst)beginif(rst=1b0)clk_div_reg=0;elsebeginif(write & ce & clk_div_reg_sel)beginif(bytesel0)clk_div_reg7:0=wrdata7:0;if(bytesel1)clk_div_reg15:8=wrdata15:8;if(bytesel2)clk_div_reg23:16=wrdata23:16;if(bytesel3)clk_div_reg31:24=wrdata31:24;endendendalways(posedge clk or negedge rst)beginif(rst=1b0)duty_cycle_reg=0;elsebeginif(write&ce&duty_cycle_reg_sel)beginif(bytesel0)duty_cycle_reg7:0=wrdata7:0;if(bytesel1)duty_cycle_reg15:8=wrdata15:8;if(bytesel2)duty_cycle_reg23:16=wrdata23:16;if(bytesel3)duty_cycle_reg31:24=wrdata31:24;endendendalways(posedge clk or negedge rst)beginif(rst=1b0)control_reg=0;elsebeginif(write & ce & control_reg_sel)beginif(bytesel0)control_reg=wrdata0;endendendalways(addr or read or clk_div_reg or duty_cycle_reg or control_reg or ce)beginif(read & ce)case(addr)2b00:rddata=clk_div_reg;2b01:rddata=duty_cycle_reg;2b10:rddata=clk_div_reg)pwm_cnt=0;elsepwm_cnt=pwm_cnt+1;endelsepwm_cnt=0;endendalways(posedge clk or negedge rst)beginif(rst=1b0);elsebeginif(pwm_e