多位8段数码管的控制.ppt

数码管的控制 设计一个电子时钟 数码管外观 各种各样的数码管 共阴 共阳 原理图 FPGA相关引脚 set location assignmentPIN 239 toseg 0 Aset location assignmentPIN 224 toseg 1 Bset location assignmentPIN 227 toseg 2 Cset location assignmentPIN 236 toseg 3 Dset location assignmentPIN 237 toseg 4 Eset location assignmentPIN 234 toseg 5 Fset location assignmentPIN 226 toseg 6 Gset location assignmentPIN 233 toseg 7 Hset location assignmentPIN 221 tosegcs 0 set location assignmentPIN 222 tosegcs 1 set location assignmentPIN 223 tosegcs 2 set location assignmentPIN 225 tosegcs 3 set location assignmentPIN 228 tosegcs 4 set location assignmentPIN 235 tosegcs 5 set location assignmentPIN 238 tosegcs 6 set location assignmentPIN 240 tosegcs 7 译码 process second0 begincasesecond0iswhen 0000 sec0Seg 7downto0 sec0Seg 7downto0 sec0Seg 7downto0 sec0Seg 7downto0 sec0Seg 7downto0 sec0Seg 7downto0 sec0Seg 7downto0 sec0Seg 7downto0 sec0Seg 7downto0 sec0Seg 7downto0 sec0Seg 7downto0 11111111 endcase endprocess 多位控制 process clk fresh 位选信号 扫描时间1MS variablecnt std logic vector 2downto0 beginif clk fresh eventandclk fresh 1 thencnt cnt 1 ifcnt 001 thensegcs 00010000 seg min1Seg minelsifcnt 010 thensegcs 00001000 seg min0Seg 计时器 Process clk 1hz BeginIfclk 1hz eventandclk 1hz 1 thenifsec0 9thensec0 sec0 1 elsesec0 0 ifsec1 5thensec1 sec1 1 elsesec1 0 ifmin0 9thenmin0 min0 1 elsemin0 0 ifmin1 5thenmin1 min1 1 elsemin1 0 ifhour0 9thenhour0 hour0 1 elsehour0 0 ifhour1 2thenhour1 hour1 1 elsehour1 0 endif 时钟准备 process clk 1KHZ 用于数码管扫描信号variablecnt integerrange0to50000 定时1MSbeginifclk eventandclk 1 thencnt cnt 1 ifcnt 25000thenclk fresh 1 elsifcnt 50000thenclk fresh 0 elsecnt 0 clk fresh 0 endif endif endprocess process clk fresh 此进程产生1S的脉冲信号 clk fresh为1K的脉冲信号 variablecnt integerrange0to1000 beginifclk fresh eventandclk fresh 1 thencnt cnt 1 ifcnt 50