基于Verilog的mx25L1605A(Serial Flash)模型.doc

/*-* mx25L1605A.v - 16M-BIT CMOS Serial Flash* COPYRIGHT 2005 BY Macronix International Corporation*-* Creation Date: 2005/5/* Doc: REV.0.00, MAY. 11, 2005* VERSION : V 0.01* Note : This model do not include test mode * Description : * module flash_16m - behavior model for the 16M serial flash*-*/timescale 1ns / 1ps / Define controller state define STANDBY_STATE 0 define ACTION_STATE 1 define CMD_STATE 2 define BAD_CMD_STATE 3 define SECTOR_ERASE_TIME 90_000_000 / 90 ms define BLOCK_ERASE_TIME 1_000_000_000 / 1 s define CHIP_ERASE_TIME 32_000_000 / 32 s define PROG_TIME 1_400_000 / 1.4 ms / Time delay to write instruction define PUW_TIME 10_000_000 / 10 ms define MX25L1605A /MX25L4005ifdef MX25L4005 define FLASH_ADDR 19 define SECTOR_ADDR 7 define BLOCK_ADDR 4else ifdef MX25L1605A define FLASH_ADDR 21 define SECTOR_ADDR 9 define BLOCK_ADDR 5 endif endif define FLASH_TYPE 0module flash_16m( SCLK, CS, SI, SO, WP, HOLD); /- / Declaration of ports (input,output, inout) /- input SCLK, / Signal of Clock Input CS, / Chip select (Low active) SI, / Serial Data Input WP, / Write Protection:connect to GND HOLD; / output SO; / Serial Data Output /- / Declaration of parameter (parameter) /- parameter FLASH_SIZE = 1 FLASH_ADDR, / 2M bytes SECTOR_SIZE = 1 12, / 4K bytes BLOCK_SIZE = 1 PUW_TIME ) begin if ( CS = 1b0 ) begin si_reg 256*8-1:0 = si_reg 256*8-2:0 , SI ; end end end /*-*/ /* chip erase process */ /*-*/ always ( posedge chip_erase_oe ) begin chip_erase_count = 0; for ( chip_erase_count = 0;chip_erase_count=CHIP_ERASE_TIME;chip_erase_count=chip_erase_count+1) begin #1000; end /WIP : write in process bit chip_erase_count = 0; for( chip_erase_count = 0; chip_erase_count FLASH_SIZE; chip_erase_count = chip_erase_count+1 ) begin ROM_ARRAY chip_erase_count = 8hff; end chip_erase_count = 0; /WIP : write in process bit status_reg0 = 1b0;/WIP /WEL : write enable latch status_reg1 = 1b0;/WEL chip_erase_oe = 1b0; end /*-*/ /* Finite state machine to control Flash operation */ /*-*/ always ( posedge SCLK or posedge CS ) begin if ( CS = 1b1 ) begin / Chip Disable state = #(tC-1) STANDBY_STATE; SO_reg = #tCLQV 1bz; end else begin / Chip Enable case ( state ) STANDBY_STATE: begin SO_reg = #tCLQV 1bz; dummy_cycle( 6 ); state = #(tC-1) CMD_STATE; end CMD_STATE: begin /每8个SCLK进入CMD_STATE一次 #1; if ( si_reg 7:0 = WREN ) begin /$display( $stime, Enter Write Enable Function .); write_enable; /$display( $stime, Leave Write Enable Function .); state = STANDBY_STATE; end else if ( si_reg 7:0 = WRDI ) begin /$display( $stime, Enter Write Disable Function .); write_disable; /$display( $stime, Leave Write Disable Function .); state = STANDBY_STATE; end else if ( si_reg 7:0 = RDID ) begin /$display( $stime, Enter Read ID Function .); read_id; /$display( $stime, Leave Read ID Function .); state = STANDBY_STATE; end else if ( si_reg 7:0 = RDSR ) begin /$display( $stime, Enter Read Status Function .); read_status ( status_reg ); /$display( $stime, Leave Read Status Function .); state = STANDBY_STATE; end else if ( si_reg 7:0 = WRSR ) begin /$display( $stime, Enter Write Status Function .); write_status; /$display( $stime, Leave Write Status Function .); state = STANDBY_STATE; end else if ( si_reg 7:0 = READ ) begin $display( $stime, Enter Read Data Function .); dummy_cycle( 24 ); / to get 24 bits address read_data; /$display( $stime, Leave Read Data Function .); state = STANDBY_STATE; end else if ( si_reg 7:0 = FASTREAD ) begin /$display( $stime, Enter Fast Read Data Function .); dummy_cycle( 24 ); / to get 24 bits address fast_read_data; /$display( $stime, Leave Fast Read Data Function .); state = STANDBY_STATE; end /else if ( si_reg 7:0 = PARALLELMODE ) begin / /$display( $stime, Enter Parallel Mode Function .); / parallel_mode; / /$display( $stime, Leave Parallel Mode Function .); / state = STANDBY_STATE; /end else if ( si_reg 7:0 = SE ) begin /$display( $stime, Enter Sector Erase Function .); dummy_cycle( 24 ); / to get 24 bits address sector_erase; /$display( $stime, Leave Sector Erase Function .); state = STANDBY_STATE; end else if ( si_reg 7:0 = BE ) begin /$display( $stime, Enter Block Erase Function .); dummy_cycle( 24 ); / to get 24 bits address block_erase; /$display( $stime, Leave Block Erase Function .); state = STANDBY_STATE; end else if ( si_reg 7:0 = CE1 | si_reg 7:0 = CE2 ) begin /$display( $stime, Enter Chip Erase Function .); chip_erase; /$display( $stime, Leave Chip Erase Function .); state = STANDBY_STATE; end else if ( si_reg 7:0 = PP ) begin /$display( $stime, Enter Page Program Function .); dummy_cycle( 24 ); / to get 24 bits address setup_addr( si_reg, segment_addr, offset_addr ); page_program( segment_addr, offset_addr ); update_array( segment_addr, offset_addr ); /$display( $stime, Leave Page Program Function .); state = STANDBY_STATE; end else if ( si_reg 7:0 = DP ) begin /$display( $stime, Enter Deep Power Dwon Function .); deep_power_down; /$display( $stime, Leave Deep Power Down Function .); state = STANDBY_STATE; end /else if ( si_reg 7:0 = EN4K ) begin / /$display( $stime, Enter Enter 4Kb Sector Function .); / enter_4kb_sector; / /$display( $stime, Leave Entor 4Kb Sector Function .); / state = STANDBY_STATE; /end /else if ( si_reg 7:0 = EX4K ) begin / /$display( $stime, Enter Exit 4Kb Sector Function .); / exit_4kb_sector; / /$display( $stime, Leave Exit 4Kb Sector Function .); / state = STANDBY_STATE; /end else if ( si_reg 7:0 = RDP | si_reg 7:0 = RES ) begin /$display( $stime, Enter Release from Deep Power Dwon Function .); release_from_deep_power_dwon; /$display( $stime, Leave Release from Deep Power Dwon Function .); state = STANDBY_STATE; end else if ( si_reg 7:0 = REMS ) begin /$display( $stime, Enter Read Electronic Manufacturer & ID Function .); dummy_cycle ( 16 ); / 2 dummy cycle dummy_cycle ( 8 ); / 1 AD read_electronic_manufacturer_device_id; /$display( $stime, Leave Read Electronic Manufacturer & ID Function .); state = STANDBY_STATE; end else begin state = #1 BAD_CMD_STATE; end end BAD_CMD_STATE: begin /SO = #tSHQZ 1bz; SO_reg = #tSHQZ 1bz; state = #(tC-1) BAD_CMD_STATE; end default: begin SO_reg = #tAA 1bx; state = #(tC-1) STANDBY_STATE; end endcase end / else begin end / always ( posedge SCLK or posedge CS ) begin / / Module Task Declaration / /*-*/ /* Description: define a wait dummy cycle task */ /* INPUT */ /* cnum: cycle number */ /*-*/ task dummy_cycle; input 31:0 cnum; begin repeat( cnum ) begin ( posedge SCLK ); end end endtask /*-*/ /* Description: setup segment address and offset address from */ /* 4-byte serial input. */ /* INPUT */ /* si: 4-byte serial input */ /* OUTPUT */ /* segment: segment address */ /* offset : offset address */ /*-*/ task setup_addr; input 23:0 si; output 13:0 segment; output 7:0 offset; begin #1; offset 7:0 = si_reg 7:0 ; segment 13:0 = si_reg 23:8 ; e