eda练习题1.doc

1、优先级编码器。图是一个7级优先级编码器。如果输入矢量中出现多个1，那么电路将优先对最高位编码输出。000表示输入矢量中没有出现位1，不需要编码输出。使用WHEN/ELSE语句实现该电路。LIBRARY ieee; USE ieee.std_logic_1164.all;ENTITY encoder IS PORT ( x: IN bit_VECTOR(7 DOWNTO 1); y: OUT bit_VECTOR(2 DOWNTO 0);END encoder; ARCHITECTURE encoder1 OF encoder ISBEGIN y = 111 WHEN x(7)=1ELSE 110 WHEN x(6)= 1 ELSE 101 WHEN x(5)= 1 ELSE 100 WHEN x(4)= 1 ELSE 011 WHEN x(3)= 1ELSE 010 WHEN x(2)= 1 ELSE 001 WHEN x(1)= 1 ELSE 000 ; END encoder1;2、编写实现如图所示状态转移关系的VHDL代码。library ieee;use ieee.std_logic_1164.all;entity fsm isport( inp,rst,clk:in std_logic; outp:out std_logic_vector(1 downto 0);end fsm;architecture arch of fsm istype state is(state1,state2,state3,state4);signal pr_state,nx_state:state;signal temp:std_logic_vector(1 downto 0);begin process(rst,clk) begin if(rst=1) then pr_state=state1; elsif(clkevent and clk=1) then outp=temp; pr_state temp=00; if(inp=1) then nx_state=state2; else nx_state temp=01; if(inp=0) then nx_state=state3; else nx_state temp=10; if(inp=1) then nx_state=state4; else nx_state temp=11; if(inp=1) then nx_state=state1; else nx_state=state2; end if; end case; end process;end arch;3、通用奇偶校验发生器电路当输入矢量中1的个数分别为奇数和偶数时，所增加的输出位的值相应地为1和0，这样使得输出矢量中1的个数恒为偶数。1 -2 ENTITY parity_gen IS3 GENERIC (n: INTEGER := 7); 4 PORT ( input: IN BIT_VECTOR(n-1 DOWNTO 0); 5 output: OUT BIT_VECTOR(n DOWNTO 0); 6 END parity_gen; 7 -8 ARCHITECTURE parity OF parity_gen IS9 BEGIN10 PROCESS (input)11 VARIABLE temp1: BIT; 12 VARIABLE temp2: BIT_VECTOR(outputRANGE); 13 BEGIN14 temp1 := 0; 15 FOR i IN inputRANGE LOOP16 temp1 := temp1 XOR input(i); 17 temp2(i) := input(i); 18 END LOOP; 19 temp2(outputHIGH ) := temp1;20 output digit1 digit1 digit1 digit1 digit1 digit1 digit1 digit1 digit1 digit1 NULL; 43 END CASE; 44 CASE temp2 IS 45 WHEN 0 = digit1 digit1 digit1 digit1 digit1 digit1 digit1 digit1 digit1 digit1 NULL; 56 END CASE; 57 END PROCESS; 58 END counter; 5、使用loop语句实现对输入矢量中连续出现的零的个数进行统计1 - 2 LIBRARY ieee; 3 USE ieee.std_logic_1164.all; 4 -5 ENTITY LeadingZeros IS6 PORT ( data: IN STD_LOGIC_VECTOR(7 DOWNTO 0); 7 zeros: OUT INTEGER RANGE 0 TO 8); 8 END LeadingZeros; 9 -10 ARCHITECTURE behavior OF LeadingZeros IS11 BEGIN12 PROCESS (data)13 VARIABLE count: INTEGER RANGE 0 TO 8; 14 BEGIN15 count := 0; 16 FOR i IN dataRANGE LOOP17 CASE data(i) IS18 WHEN 0 = count := count+1; 19 WHEN OTHERS = EXIT; 20 END CASE; 21 END LOOP; 22 zeros = count; 23 END PROCESS; 24 END behavior;6、设计一个对时钟进行6分频的电路1 -2 LIBRARY ieee; 3 USE ieee.std_logic_1164.all; 4 -5 ENTITY freq_divider IS6 PORT (clk: IN STD_LOGIC; 7 out1, out2: BUFFER STD_LOGIC); 8 EDN freq_divider; 9 -10 ARCHITECTURE example OF freq_divider IS11 SIGNAL count1: INTEGER RANGE 0 TO 7; 12 BEGIN13 PROCESS (clk)14 VARIABLE count2: INTEGER RANGE 0 TO 7; 15 BEGIN16 IF (clkEVENT AND clk = 1) THEN17 count1 = count1+1; 18 count2 := count2+1; 19 IF (count1 =?) THEN20out1 = NOT out1; 21count1 = 0; 22 END IF; 23 IF (coun2=?) THEN24out2 = NOT out2; 25count2 := 0; 26 END IF27 END IF; 28 END PROCESS; 29 END example;Count1=2 count2=37、信号发生器ENTITY sig IS PORT (clk: IN BIT; out1,out2: buffer BIT); END sig; ARCHITECTURE sig OF sig IS TYPE state IS (one, two, three,four); SIGNAL pr_state1, nx_state1: state; SIGNAL pr_state2, nx_state2: state; SIGNAL pr_state3, nx_state3: state; SIGNAL out3, out4,out5: BIT; BEGINPROCESS (clk) BEGIN IF (clkEVENT AND clk = 1) THEN pr_state1 = nx_state1; END IF; END PROCESS; PROCESS (clk)BEGIN IF (clkEVENT AND clk = 1) THEN pr_state2 = nx_state2; END IF; END PROCESS; PROCESS (clk)BEGIN IF (clkEVENT AND clk = 0) THEN pr_state3 out1 = 1; nx_state1 out1 = 0; nx_state1 out1 = 0; nx_state1 out1 = 0; nx_state1 out3 = 0; nx_state2 out3 = 1; nx_state2 out3 = 0; nx_state2 out3 = 0; nx_state2 out4 = 0; nx_state3 out4 = 1; nx_state3 out4 = 0; nx_state3 out4 = 0; nx_state3 = one; END CASE; END PROCESS; out5= out3 and out4;out2= out1 or out5;end sig;8、设计一个自动售货机的控制器电路。该自动售货机销售价格为25美分的糖果。控制器的输入和输出如图所示。输入信号是nickel_in（投入5美分），dime_in（投入10美分）和quarter_in（存放25美分）。另外两个必要的输入是clk（时钟）和rst（复位）。控制器相应地有3个输出：candy_out用于控制发放糖果，nickel_out用于控制找回5美分的零钱，dime_out用于控制找回10美分零钱。1 -2 LIBRARY ieee; 3 USE ieee.std_logic_1164.all; 4 -5 ENTITY vending_machine IS6 PORT (clk, rst: IN STD_LOGIC; 7 nickel_in, dime_in, quarter_in: IN BOOLEAN; 8 candy_out, nickel_out, dime_out: OUT STD_LOGIC); 9 END vending_machine; 10 -11 ARCHITECTURE fsm OF vending_machine IS12 TYPE state IS (st0, st5, st10, st15, st20, st25, 13 st30, st35, st40, st45); 14 SIGNAL present_state, next_state: STATE; 15 BEGIN16 -Lower section of the FSM (Sec.8.2): -17 PROCESS (rst, clk)18 BEGIN19 IF (rst = 1) THEN20 present_state = st0; 21 ELSIF (clkEVENT AND clk = 1) THEN22 present_state 30 candy_out = 0; 31 nickel_out = 0; 32 dime_out = 0; 33 IF (nickel_in) THEN next_state = st5; 34 ELSIF (dime_in) THEN next_state = st10; 35 ELSIF (quarter_in) THEN next_state = st25; 36 ELSE next_state 39 candy_out = 0; 40 nickel_out = 0; 41 dime_out = 0; 42 IF (nickel_in) THEN next_state = st10; 43 ELSIF (dime_in) THEN next_state = st15; 44 ELSIF (quarter_in) THEN next_state = st30; 45 ELSE next_state 48 candy_out = 0; 49 nickel_out = 0; 50 dime_out = 0; 51 IF (nickel_in) THEN next_state = st15; 52 ELSIF (dime_in) THEN next_state = st20; 53 ELSIF (quarter_in) THEN next_state = st35; 54 ELSE next_state 57 candy_out = 0; 58 nickel_out = 0; 59 dime_out = 0; 60 IF (nickel_in) THEN next_state = st20; 61 ELSIF (dime_in) THEN next_state = st25; 62 ELSIF (quarter_in) THEN next_state = st40; 63 ELSE next_state 66 candy_out = 0; 67 nickel_out = 0; 68 dime_out = 0; 69 IF (nickel_in) THEN next_state = st25; 70 ELSIF (dime_in) THEN next_state = st30; 71 ELSIF (quarter_in) THEN next_state = st45; 72 ELSE next_state 75 candy_out = 1; 76 nickel_out = 0; 77 dime_out = 0; 78 next_state 80 candy_out = 1; 81 nickel_out = 1; 82 dime_out = 0; 83 next_state 85 candy_out = 1; 86 nickel_out = 0; 87 dime_out = 1; 88 next_state 90 candy_out = 0; 91 nickel_out = 1; 92 dime_out = 0; 93 next_state 95 candy_out = 0; 96 nickel_out = 0; 97 dime_out = 1; 98 next_state 0); 21 temp := 0; 22 err = 0; 23 data_vaild = 0; 24 ELSIF (clkEVENT AND clk = 1) THEN25 IF (reg(0) = 0 AND din = 1) THEN26 reg(0) := 1; 27 ELSIF (reg(0) = 1) THEN28 count := count+1; 29 IF (count10) THEN30 reg(count) := din; 31 ELSIF (count=10) THEN32 temp := (reg(1)XOR reg(2)XOR reg(3)XOR33 reg(4)XOR reg(5)XOR reg(6)XOR34 reg(7)XOR reg(8)OR NOT reg(9); 35 err = temp; 36 count := 0; 37 reg(0) := din; 38 IF (temp = 0) THEN39 data_vaild = 1; 40 data B ) then Y = 001; elsif ( A = B) then Y = 010; else Y d2)、f2(d1=d2)、f3(d1d2 then f1=1; else f1=0; end if; if d1=d2 then f2=1; else f2=0; end if; if d1d2 then f3=1; else f3=0; end if; end process;end;12、设计一个二-十进制BCD译码器。译码器输入din为4位二进制数，输出为4位二进制数表示的两个十进制数a、b。源程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity v2_bcdymq is port(din:in integer range 15 downto 0; a,b:out integer range 9 downto 0);end;architecture fpq1 of v2_bcdymq is beginp1:process begin if din10 then a=din; b=0; else a=din-1-10; b=1; end if;end process p1;end;13、设计一个计时器，它能从0秒计时到9分59秒（见图），当前时间可以在SSD（7段数码显示器）上显示。要求电路具有启动和复位按钮，时钟频率为1 Hz。- LIBRARY ieee; USE ieee.std_logic_1164.all; - ENTITY fen IS PORT ( clk, reset,start: IN STD_LOGIC; s1, s2,m1: OUT integer range 0 to 10); END fen; - ARCHITECTURE counter OF fen IS BEGIN PROCESS (clk, reset,start) VARIABLE ts2,ts1,tm1: INTEGER RANGE 0 TO 10; BEGIN -counter: - IF (reset = 1) THEN ts1 := 0; ts2 := 0; tm1 := 0; elsif(start=1)then IF (clkEVENT AND clk = 1) THEN ts1 := ts1+1; IF (ts1=10) THEN ts1 := 0; ts2 := ts2+1; IF (ts2=6) THEN ts2 := 0; tm1 := tm1+1; IF (tm1=10) THEN tm1 := 0; end if; END IF; END IF; end if; END IF; s1=ts1; s2=ts2; m1=tm1; END PROCESS; END counter;14、并/串转换器的电路结构如图所示。d(7: 0)是需要发送的并行数据，dout上是真正串行输出的数据。另外还有两个输入：clk和load。当load有效时，并行输入数据d(7: 0)被同步存储在移位寄存器中。当load保持为高时，MSB，即d(7)在输出端始终保持有效。一旦load返回0，接下来移位寄存器的各个位将在每个时钟上升沿依次出现在输出端口dout上。8位数据全部发送完毕之后，输出端在下一次数据传输之前一直保持为低电平。1 -2 LIBRARY ieee; 3 USE ieee.std_logic_1164.all; 4 -5 ENTITY serial_converter IS6 PORT (d: IN STD_LOGIC_VECTOR(7 DOWNTO 0); 7 clk, load: IN STD_LOGIC; 8 dout: OUT STD_LOGIC); 9 END serial_converter; 10 -11 ARCHITECTURE serial_converter OF serial_converter IS12 SIGNAL reg: STD_LOGIC_VECTOR(7 DOWNTO 0); 13 BEGIN14 PROCESS (clk)15 BEGIN16 IF (clkEVENT AND clk = 1) THEN17 IF (load = 1) THEN reg = d; 18 ELSE reg = reg