AD7656verilog状态机.doc

module adc(data,clk,Busy,cs_n,convsta,convstb,convstc,rd,databuf);input 15:0 data;/?input clk,Busy;output convsta,convstb,convstc;/?output rd,cs_n;output 15:0 databuf;/?reg rd;reg 15:0 REGL;reg convsta,convstb,convstc;wire cs_n;wire 15:0 databuf;parameter st0=4b0000, st1=4b0001, st2=4b0010, st3=4b0011, st4=4b0100, st5=4b0101;parameter st6=4b0110, st7=4b0111, st8=4b1000, st9=4b1001, st10=4b1010, st11=4b1011;parameter st12=4b1100, st13=4b1101;reg 3:0 current_states, next_states; assign cs_n= 0; assign databuf= REGL; always(posedge clk) begin current_states= next_states; end always(*) begin case(current_states) st0:begin/ ? convsta= 0; convstb= 0; convstc=0; next_states=st1; rd=1b1; end st1:begin/?AD? convsta= 1; convstb=1; convstc= 1; next_states= st2; rd= 1; end st2:begin/? convsta=0; convstb= 0; convstc=0; rd= 1; if(Busy=0) begin next_states= st3; rd=1; end else next_states= st2; end st3: begin /? convsta= 0; convstb= 0; convstc=0; rd=0; REGL = data; next_states= st4; end st4: begin /?RD convsta= 0; convstb= 0; convstc=0; rd=1; next_states= st5; end st5: begin/? convsta= 0; convstb= 0; convstc=0; next_states= st6; rd=0; REGL = data; end st6: begin /?RD convsta= 0; convstb= 0; convstc=0; rd=1; next_states= st7; end st7: begin /? convsta= 0; convstb= 0; convstc=0; next_states= st8; rd=0; REGL = data; end st8: begin /?RD convsta= 0; convstb= 0; convstc=0; rd=1; next_states= st9; end st9: begin /? convsta= 0; convstb= 0; convstc=0; next_states= st10; rd=0; REGL = data; end st10: begin /?RD convsta= 0; convstb= 0; convstc=0; rd=1; next_states= st11; end st11: begin /? convsta= 0; convstb= 0; convstc=0; next_states= st12; rd=0; REGL = data; end st12: begin /?RD convsta= 0; convstb= 0; convstc=0; rd=1; next_states= st13; end st13: begin /? convsta= 0; convstb= 0; convstc=0; next_states= st0; rd