Hardware Software Co-Design A Case Study of Next Generation Single Chip PDA.ppt

Hardware SoftwareCo Design ACaseStudyofNextGenerationSingleChipPDA R C ChangDepartmentofComputerandInformationScienceNationalChiaoTungUniversity Outline IntroductionCadenceVirtualComponentCo DesignSingleChipPDAModelingHardware SoftwareTrade OffsConclusion DesignSpaceExploration CadenceTM Hardware SoftwareRepresentations VariousmodelscontainstrongpropertiesthatmightbeusefulforsomeapplicationsPropertiesTiming ClockMechanism CommunicationMethod Hierarchy Determinism MathFormalismComputationModel FiniteStateMachine DiscreteEventSystem CommunicatingProcesses PetriNets Synchronous ReactiveModels Control DataflowGraphics CiertoVirtualComponentCo Design ToolfromCadenceDesignSystemBasedonPOLISProjectofUCBEECSUseCodesignFiniteStateMachinerepresentationmodelAfront endforSoCdesignflow VirtualComponentCo Design BenefitfromIPsreuseSystemLevelIPsIntegrationExplorepartitioningtrade offsbeforesynthesisSeparateasystemintoBehavior function application andArchitectureSeparateamodelintofunctionandperformance ConventionalHW SWCo Design VCCDesignFlow WirelessMultimediaPDA BaseStation Wire Wireless PC PDA PDAModeling HeavyApplication Function Behavior Videoplayback MPEG4VideoVideoPhone H 324 M Video H 263 ArchitectureSingleChipProcessor DSP optional Bus BridgeRAM Flash Peripheral H 263CodecBlockDiagram H 263BehaviorDiagram Bitstream Packet Packet Bitstream YUV RGB 10Hz YUV FunctionalSimulationModel ModelDefinition Inputports Outputports Parameters Implementation CreateVCCTypes ports parameters YUVFrame RGBFrame PacketCreateEncoder DecoderBlocksCreateWhiteboxCmodelfromCprojectTMN 2 0 H 263ver 1baselinecodec InteractwithexternalviaportmanipulationEmbeddedWaitsAPI Implementation cont CreatePacketizer De PacketizerConvertbetweenBitstreamandPacketCreateSensor Display NetBlocksConnectsimulationtoWin32environmentSensor ReadYUVFramesfromfileDisplay DisplayFramewithWin32GDINet BufferPacketandsimulatenetwork PerformanceModel i B i o p o p Functionalmodel Performancemodel Inputdelay Outputdelay PDAArchitecture PeripheralBus ArchitectureDiagram Processor ModifiedfromARM7TDMImodelARM922T ARM9TDMI 8KI Cache 8KD Cache MMUCache 8Kbytes 256linesof32bytes 64wayset associative RTLinux InterruptLatency 10usforembeddedprocessor RTLinux SchedulingLatency4ms RTSS2000 2 6ms MailingList Hardware SoftwarePartitioning MaptoRTOSSoftwareMaptoASICHardwareHexagramCommunicationPattern ARM9Core SoftwarewithmicroprocessorImpossibletoencodevideoinrealtimeAthlon500 FreeBSD4 3R GCC2 95 3 341framesdataOptimizedwith O2 49 92secNon Optimized 110 48sec ARM9 DSPExtension ARM922T TITMS320C6200ManualAnnotatedPerformanceModelEncoderProfileSADOptimization ARM9 ASICcodec ASICperformancemodelcanonlybecreatedmanuallyASICdevelopmentisnotanissueofVCCIfoursystemcontainsaH 263codecASIC theperformanceofourcaseisdeterminedbyASICperformance SimulationResult Decoder ARM9only17MHz ARM9 DSP14MHz SimulationResult Encoder ARM DSP180MHz SimulationResult FullCodec ARM DSP195MHz Conclusion ConvertaexistingCProjecttoVCCbehaviormodelCreatePDAmodelandaH 263full duplexcodecinVCCenvironmentRunpe