DC Design Compiler 综合脚本命令及参考模板.doc

Design Compiler 综合脚本常用命令和模板参照自己的设计，以及自己的工艺信息，适当修改下面的Constraints 和 Run Script 等的脚本，添加一些相关的约束语句，就可以运行了详细的命令请参照DC的官方User Guide等相关资料。Invoking Design CompilerUnix% design_vision # Interactive GUI, WLM modeUnix% design_vision topographical # Interactive GUI, Topographical modeUnix% dc_shell-t # Interactive shell, WLM modeUnix% dc_shell-t topographical # Interactive shell, Topographical modeUnix% dc_shell-t f RUN.tcl | tee i my.log # Batch mode.synopsys_dc.setup set search_path “$search_path libs cons unmapped rtl”set synthetic_library dw_foundation.sldb set target_library 65nm.dbset link_library “* $target_library $synthetic_library IP.db”set symbol_library 65nm.sdbdefine_design_lib WORK path ./workset_svf set_vsdc history keep 200set sh_enable_page_mode false set cache_write .set cache_read $cache_write suppress_message LINT-28 LINT-32 LINT-33 UID-401 set alib_library_analysis_path get_unix_variable HOMEalias h historyalias rc “report_constraint -all_violators”TCL Commands and Constructsset PER 2.0# Define a variable and its valueecho $PER# Variable substitution 2.0 set MARG 0.95expr $PER * $MARG# expr: *, /, +, -, , , =, =set pci_ports get_ports A# Imbedded commandset pci_ports get_ports “Y?M Z*”# Wildcardsecho “Effctv P = # Soft quotes 1.9 expr $PERIOD * $MARGIN”echo Effctv P = # Hard quotes expr $PERIOD * $MARGIN# Effctv P = expr $PER * $MARG# Comment lineset COMMENT in_line;# In-line commentset MY_DESIGNS B1.v . B26.v # foreach loopforeach DESIGN $MY_DESIGNS read_verilog $DESIGNfor set i 1 $i 27 incr i # for loop read_verilog BLOCK_$i.v Helpful UNIX-like DC-shell commands pwd cd ls history! !7!reportsh printenv get_unix_variable ARCHConstraintsreset_design set_max_area 0 create_clock -period 2 name Main_Clk get_ports Clk1create_clock period 2.5 waveform 2 3.5 get_ports Clk2create_clock period 3.5 name V_Clk; # VIRTUAL clockset_clock_uncertainty setup 0.14 get_clocks *set_clock_uncertainty setup 0.21 from get_clocks Main_Clk to get_clocks Clk2set_clock_latency max 0.6 get_clocks Main_Clkset_clock_latency source max 0.3 get_clocks Main_Clkset_clock_transition 0.08 get_clocks Main_Clkset_input_delay -max 0.6 -clock Main_Clk all_inputsset_input_delay max 0.3 clock Clk2 clock_fall add_delay get_ports “B E”set_input_delay -max 0.5 -clock network_latency_included V_Clk get_ports “A C F”set_output_delay -max 0.8 -clock source_latency_included Main_Clk all_outputsset_output_delay -max 1.1 -clock V_Clk get_ports “OUT2 OUT7set_max_capacitance 1.2 all_inputsset_load 0.080 all_outputsset_load expr load_of slow_proc/NAND2_3/A * 4 get_ports OUT3set_load 0.12 all_inputsset_input_transition 0.12 remove_from_collection all_inputsget_ports Bset_driving_cell lib_cell FD1 pin Q get_ports Bset_operating_conditions max WCCOMset auto_wire_load_selection falseset_wire_load_model name 1.6MGatesset_wire_load_mode enclosedset_wire_load_model name 200KGates get_designs “SUB1 SUB2”set_wire_load_model name 3.2MGates get_ports IN_Aset_port_fanout_number 8 get_ports IN_Aset_false_path -from get_clocks Asynch_CLKA -to get_clocks Asynch_CLKBset_multicycle_path setup 4 from from A_reg -through U_Mult/Out to B_reg set_multicycle_path hold 3 from from A_reg -through U_Mult/Out to B_reg set_isolate_ports type inverter all_outputsset_ideal_network get_ports reset* select*set_ideal_network get_pins FF_SET_reg/Qset_ideal_network no_propagate get_nets CTRLset_ideal_latency 1.4 get_ports reset* select* set_ideal_transition 0.5 get_pins FF_SET_reg/Qset_scan_configuration -style Checking and Removing Constraints and Directivesreport_clock; report_clock -skewreport_design report_port verbosereport_wire_load report_path_groups report_timing_requirements (ignored)report_auto_ungroup report_isolate_ports write_script output check_timing reset_path from FF1_regremove_clock remove_clock_transition remove_clock_uncertainty remove_input_delay remove_output_delay remove_driving_cell remove_wire_load_model Syntax CheckingUnix% dcprocheck constr_file.conPhysical Constraints Topographical Modeset_aspect_ratio set_utilizationset_placement_area set_rectilinear_outline set_port_side set_port_location set_cell_location create_placement_keepout Misc. Reports # Generate A library report fileread_db library_file.db list_libs redirect file reports/lib.rpt report_lib report_hierarchy -noleaf # Arithmetic implementation and # resource-sharing info report_resources # List area for all cells in the designreport_cell get_cells hier *Run Scriptread_verilog A.v B.v TOP.vorread_vhdl A.vhd B.vhd TOP.vhdorread_ddc MY_TOP.ddcoracs_read_hdl MY_TOPoranalyze format verilog A.v B.v TOP.velaborate MY_TOP parameters “A_WIDTH=8, B_WIDTH=16”current_design MY_TOPlinkif check_design =0 echo “Check Design Error” exit# Exits DC if a check-design error is encountered# Continue if NO problems encounteredwrite f ddc hier out unmappedd/TOP.ddcredirect tee file reports/precompile.rpt source echo -verbose TOP.conredirect append tee file reports/precompile.rpt check_timingsource or # Source tcl constraints, if available, orextract_physical_constraints # Extract and apply from an existing # DEF floorplan filegroup_path -name CLK1 -critical_range weight 5group_path -name CLK2 -critical_range weight 2group_path name INPUTS from all_inputsgroup_path name OUTPUTS to all_outputsgroup_path name COMBO from all_inputs to all_outputsset_fix_multiple_port_nets all buffer_constants* * Insert Expert, Ultra or ACS compile flow here * *check_design report_constraint all_violators report_timing delay to from through input_pins max_paths nworst nets cap sig groupreport_area report_qor set verilogout_no_tri truechange_names rule verilog hier write f verilog hier out mapped/TOP.v write f ddc hier out mapped/TOP.ddcwrite_sdc TOP.sdcwrite_scan_def out TOP_scan.defwrite_physical_constraints output TOP_PhysConstr.tclexitObject Retrieval and Manipulation (Collection Commands)get_ports, get_pins, get_designs get_cells, get_nets, get_clocks get_nets of_objects get_pins FF1_reg/Qget_libs get_lib_cells get_lib_pins all_inputs, all_outputs, all_clocks, all_registers all_connected all_fanin, all_fanout all_ideal_nets set pci_ports get_ports pci_*echo $pci_ports # _sel184query_objects $pci_ports # pci_1 pci_2 .get_object_name $pci_ports # pci_1 pci_2 .sizeof_collection $pci_ports # 37set pci_ports add_to_collection $pci_ports get_ports CTRL*set all_inputs_except_clk remove_from_collection all_inputs get_ports CLKcompare_collections index_collection sort_collection foreach_in_collection my_cells get_cells -hier * -filter “is_hierarchical = true” echo “Instance get_object_name $cell is hierarchical” # Filtering operators: =, !=, , =, =, =, !filter_collection get_cells * “ref_name = AN*”get_cells * -filter “dont_touch = true”get_clocks * -filter “period 10” # List all cell attributes and redirect output to a fileredirect file cell_attr list_attributes application class cell # Grep the file for cell attributes starting with dont_UNIX% grep dont_ cell_attr | more # List the value of the attribute dont_touch get_attribute dont_touchUltra Compile Flow - Topographical or WLM ModeUltra + DesignWare and DFTC licenses available # In “topo” mode (dc_shell-t topo) specify Milkyway reference and design librariescreate_mw_lib tech -mw_reference_library open_mw_lib set_tlu_plus_files -max_tluplus -tech2itf_map set compile_auto_ungroup_delay_num_cells 99999999 set compile_auto_ungroup_count_leaf_cells trueset compile_auto_ungroup_override_wlm trueset_ungroup false # OPTIONAL: Disable unconditional auto-ungrouping # of DesignWare hierarchy (not usually recommended)set compile_ultra_ungroup_dw false # If design contains pipelined sub-designs and the pipeline registers # are grouped together at the input or output, relax timingset_multicycle_path setup -from U_Pipeline/R3_reg* to U_Pipeline/R7_reg* # In “ topo” mode, if the floorplan is available, apply or extract the physical constraintssource ORextract_physical_constraints # OPTIONAL: Exclude specific cells/design from adaptive retiming (-retime)set_dont_retime true # First compilecompile_ultra scan retime timing|-area # The design hierarchy may have changed due to auto-ungrouping/-uniquifyingreset_path -from U_Pipeline/R3_reg* -to U_Pipeline/R7_reg* # OPTIONAL: Maintain registered pipeline outputs if requiredset_dont_touch get_cells U_Pipeline/R12_reg* true # Optimize registers if pipeline violates timing; Skip if no pipeline issues:set_optimize_registers true design My_Pipeline_Subdesignoptimize_registers only_attributed_designs # Continue if design is NOT meeting all constraints: # Apply more focus on violating critical paths, as necessarygroup_path name -from -to critical range -weight 5 # Select appropriate second compile # In “topo” mode in DC v2006.06, or any mode in DC v2007.03 or latercompile_ultra scan incremental # In “WLM” mode in DC v2006.06set_ultra_optimization truecompile boundary scan map_effort high incremental (-area_effort medium|low|none) # In “topo” mode prior to DC v2007.03: Write out updated physical constraintswrite_physical_constraints output PhysConstr.tclDFT Flow Expert or UltraDFTC license available # Prior to the first compile set the # scan cell style set_scan_configuration style . # Perform the first test-ready compilecompile boundary map high scan # ORcompile_ultra timing -scan # Continue before the next compile: # Read in the scan specification filesource scan_spec.tcl # Check for DFT rule violationsdft_drc # Preview the scan chainspreview_dft # Insert and optimize scaninsert_dft * * Execute additional Ultra/Expert optimization * techniques, as needed * * # After the final compile check the DFT QoR # and write out the scan DEF filedft_drc coverage_estimatewrite_scan_def -out Some Scan Specification Commandsset_scan_state test_ready set_dft_configuration .set_dft_signal .set_scan_path .set_scan_configuration .create_test_protocol Expert Compile FlowNo Ultra license available; DFTC license availablecompile boundary scan map_effort high # Continue if NOT meeting constraints # Note: -scan requires DFTC licensecompile boundary scan map_effort high incremental (-area_effort medium|low|none) # Continue if NOT meeting constraints: # Increase max-delay priority if OK to postpone DRC fixingset_cost_priority delay # Note: The design hierarchy may have changed due to auto- # uniquifying # Apply more focus on violating critical paths, as necessarygroup_path name -from -to critical range -weight 5 # Repartition if design is poorly partitionedgroup design -cell_name U2 U7 .ungroup start_level 2 U_NEW_CELLcompile boundary scan map_effort high incremental (-area_effort medium|low|none) # Or, can ungroup all hierarchy in lieu of group/ungroup # commands with ungroup_all compile boundary scan map_effort high incremental (-area_effort medium|low|none) ungroup_all “Pseudo Ultra” Compile FlowUltra license available; No DesignWare license availableset compile_auto_ungroup_delay_num_cells 99999999 set compile_auto_ungroup_area_num_cells 99999999 set compile_auto_ungroup_count_leaf_cells trueset compile_auto_ungroup_override_wlm trueset_ungroup false # OPTIONAL: Disable unconditional auto-ungrouping # of DesignWare hierarchy (not usually recommended)set compile_ultra_ungroup_dw false # If design contains pipelined sub-designs and the pipeline registers # are grouped together at the in