C52单片机(中 英文)介绍.doc

AT89C52介绍AT89C52 ATMEL是一种低功耗，高性能CMOS 8位单片机片内含8K byTES的可反复擦写的只读程序存储器（PEROM）。器件采用ATMEL公司的高密度、非易失性存储技术生产，与标准80C51指令系统及80C52 产品引脚兼容，片内置通用8位中央处理器（CPU ）和FLASH由存储单元，功能强大AT89C52单片适用于许多较为复杂控制应用场合。主要性能参数：与Mcs-51产品指令和引脚完全兼容。8字节可重擦写FLASH闪速存储器1000 次擦写周期全静态操作：0HZ-24MHZ三级加密程序存储器256X8字节内部RAM32个可编程I/0口线3个16 位定时计数器8个中断源可编程串行UART通道低功耗空闲和掉电模式AT89C52 提供以下标准功能：8字节FLASH闪速存储器，256字节内部RAM , 32个I/O口线，3个16 位定时计数器，一个6向量两级中断结构，一个全双工串行通信口，片内振荡器及时钟电路。同时，AT89c52可降至零赫兹的静态逻辑操作，并支持两种软件可选的节电上作模式。空闲方式停止CPU 的工作，但允许RAM，定时计数器串行通信口及中断系统继续工作。掉电方式保存RAM 中的内容，但振荡器停止工作并禁止其它所有部件工作直到下一个硬件复位.功能引脚说明：Vcc:电源电压GND:地P0：P0口是一组8位漏极开路型双向1/O 口，也即地址/数据总线复用口。作为输出口用时每位能吸收电流的方式驱动8个TTL 逻辑门电路，对端口P0 写“1”时，可作为高阻抗输入端用。P0口也可以配置为复低位地址/数据总线和内存数据访问外部程序。在这种模式下，P0具有内部上拉电阻。在FLASH由编程时，P0口接收指令字节，而在程序校验时，输出指令字节，校验时，要求外接上拉电阻。P1：P1是一个带内部上拉电阻的8位双向I/O口，Pl的输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。对端口写“1”，通过内部的上拉电阻把端口拉到高电平，此时可作输入口。作输入口使用时，因为内部存在上拉电阻某个引脚被外部信号拉低时会输出一个电流IIL，此外，Pl.0 和P1.1还可分别作为定时/计数器2 的外部计数输入（Pl.0/T2 ）和输入（P1.1/T2EX) 。 P2：P2 是一个带有内部上拉电阻的8位双向I/O口，P2的输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑电路。对端口P2写“l，通过内部的上拉电阻把端口拉到高电平，此时可作输入口，作输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（llt ）。在访问外部程序存储器或16位地址的外部数据存储器（例如执行MOvxDPTR 指令）时，P2送出高8 位地址数据。在访问8位地址的外部数据存储器、如执行MOVXRI指令）时，P2口输出P2锁存器的内容。FLASH编程或校验时，P2亦接收高位地址和一些控制信号。P3：P3口是一组带有内部上拉电阻的8位双向I/O口。P3口输出缓冲级可驱动(吸收或输出电流）4个TTL逻辑门电路。对P3口写入“1”时，它们被内部上拉电阻拉高并可作为输入端口。此时，被外部拉低的P3口将用上拉电阻输出电流（IIL) . 此外，P3口还接收一些用于FLASH闪速存储器编程和程序校验的控制信号。RST：复位输入。当振荡器工作时，RST引脚出现两个机器周期以上高电平将使单片机复位。ALE/PROG：一般情况下，ALE仍以时钟振荡频率的1/6输出固定的脉冲信号，因此它可对外输出时钟或用于定时目的。要注意的是：每当访问外部数据存储器时将跳过一个ALE脉冲。对Flash存储器编程期间，该引脚还用于输入编程脉冲(PROG)。如有必要，可通过对特殊功能寄存器（SFR）区中的8EH单元的D0位置位可禁止ALE操作。该位置位后，只有一条MOVX和MOVC指令才能将ALE激活,此外，该引脚会被微弱拉高，单片机执行外部程序时，应设置ALE禁止位无效。PSEN：程序储存允许PSEN输出是外部程序存储器的读选通信号，当AT89C52由外部程序存储器取指令（或数据）时，每个机器周期两次PSEN有效，即输出两个脉冲。在此期间，当访问外部数据存储器，将跳过两次PSEN信号。EA/VPP：外部访问允许。欲使CPU 仅访问外部程序存储器(地址为0000H-FFFFH ) , EA端必须保持低电平(接地）需注怠的是：如果加密位LBI被编程，复位时内部会锁存EA端状态。如EA端为高电平（接Vcc端）。flash存储器编程时，该引脚加上+12V的编程允许电源VPP ，当然这必须是该器件是使用12V编程电压VPP 。XTAL1：振荡器反相放大器的及内部时钟发生器的输入端XTAL1：振荡器反相放大器的输出端。特殊功能寄存器：并非所有的地址都被定义，还有相当一部分没有定义。对没有定义的单元读写将是无效的，读出的数位将不确定，而写入的数据也将丢失。软件使用者不应将数据1写入未定义的单元，由于这些单元在将来的产品中可能赋予新的功能，在这种情况下，复位后这些单元数值总是“0”。定时/计数器2的控制和状态位位于T2CON和T2MOD ，寄存器对（RCA02H、RCAP2L）是定时器2在16 位捕获方式或16位自动重装载方式下的捕获/自动重装载寄存器。数据存储器AT89C52有256个字节的内部RAM , 80HFFH高128个字节与特殊功能寄存器（SFR）地址是重叠的，也就是高128字节的RAM和殊功能寄存器的地址是相同的，但物理上它们是分开的。当一条指令访问7FH以上的内部地址单元时，指令中使用的寻址方式是不同的，也即寻址方式决定是访问高128字节RAM还是访问特殊功能寄存器。如果指令是直接寻址方式则为访问特殊功能寄存器 例如，下面的直接寻址指令访问特殊功能寄存器0A0H（即P2口）地址单元。MOV 0A0H ，#data 间接寻址指令访问高128字节RAM ，例如下面的间接子址指令中，R0的内容为OAOH ，则访问数据字节地址为0A0H , 而不是P2口（0A0H ）。 MOV RO ，#data堆栈操作也是间接寻址方式，所以，高128位数据RAM亦可作为堆栈区使用。定时器O和定时器1AT89C52的定时器O和定时器1的工作方式与AT89C51相同。定时器2定时器2是一个16位定时计数器。它既可当定时器使用，也可作为外部事件计数器使用，其工作方式由特殊功能寄存器T2CON的C/T2位选择。定时器2有三种工作方式：捕获方式，自动重装载（向上或向下计数）方式和波特率发生器方式，工作方式由T2CON的控制位来选择 。定时器2由两个8位寄存器TH2和TL2组成，在定时器工作方式中，每个机器周期TL2寄存器的值加1 ，由于一个机器周期由12个振荡时钟构成，因此，计数速率为振荡频率的1/l2 。 在计数工作方式时，当T2引脚上外部输入信号产生由1至O的下降沿时，寄存器的值加1，在这种工作方式下，每个机器周期的5SP2期间，对外部输入进行采样。若在第一个机器周期中采到的值为1，而在下一个机器周期中采到的值为0 , 则在紧跟着的下一个周期的S3P1期间寄存器加l 。由于识别1至0的跳变需要2个机器周期（24个振荡周期），因此，最高计数速率为振荡频率的1/24 为确保采样的正确性，要求输入的电平在变化前至少保持一个完整周期的时间，以保证输入信号至少被采样一次捕获方式：在捕获方式下，通过T2CON控制位以EXEN2来选抒两种方式。如果ExEN2=0，定时器2是一个16位定时器或计数器，计数溢出时，对T2CON溢出标志TFZ置位，同到激活中断。如果EXEN2=1，定时器2完成相同的操作，而当T2EX引脚外部输入信号发生l至0负跳变时，也出现TH2和TL2中的值分别被捕获到RCAP2H和RCAP2L中另外，T2EX引脚信号的跳变使得T2CON中的EXF2置位，与TF2相仿，EXF2也会激活中断。自动重装载（向上或向下计数器）方式：当定时器2工作于16位自动重装载方式时，能对其编程为向上或向下计数方式，这个功能可通过特殊功能寄存器T2CON的DCEN位（允许向下计数）来选择的。复位时，DCEN位置“0 ，定时器2默认设置为向上计数。当DCEN置位时，定时器2既可向上计数也可向下计数，这取决于T2EX引脚的值，参见图5 ，当DCEN=0时，定时器2自动设置为向上计数，在这种方式下，T2CON中的EXEN2控制位有两种选择，若EXEN2，定时器2为向上计数至OFFFFH溢出，置位TF2激活中断，同时把16位计数寄存器RCAP2H和RCAP2L重装载，RCAP2H 和RCAP2L的值可由软件预置。若EXEN2=1 ，定时器2的16位重装载由溢出或外部输入端T2EX从1至0的下降沿触发。这个脉冲使EXF2置位，如果中断允许，同样产生中断。 当DCEN=1时，允许定时器2向上或向下计数。这种方式下，T2EX引脚控制计数器方向。T2EX以引脚为逻辑“1”时定时器向上计数，当计数OFFFFH向上溢出时，置位TF2，同时把16位计数寄存器RCAP2H和RCAP2L 重装载到TH2和TL2中。T2EX引脚为逻辑“0”时，定时器2向下计数当TH2和TL2中的数值等于RCAP2H 和RCAP2L中的值时，计数溢出，置位TF2,司时将OFFFFH数值重新装入定时寄存器中。当定时了计数器2向上滋出或向下溢出时，置位ExF2位。附件2：外文资料AT89C52 Chip explainsThe AT89C52 is a low-power, high-performance CMOS 8-bit microcomputrwith 8 Kbytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmels high density nonvolatile memory technology and is compatible with the industry standard 80C51 and 80C52 instruction set. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional onvolatile memory programmer.By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C52 is a powerful microcomputer, which provides a highly flexible and cost effective solution to many embedded control applications.Features： Compatible with MCS-51TM Products8 Kbytes of In-System Reprogrammable Flash MemoryEndurance: 1,000 Write/Erase CyclesFully Static Operation: 0 Hz to 24 MHzThree-Level Program Memory Lock256 x 8-Bit Internal RAM32 Programmable I/O LinesThree 16-Bit Timer/CountersEight Interrupt SourcesProgrammable Serial ChannelLow Power Idle and Power Down ModesThe AT89C52 provides the following standard features: 8 Kbytes of Flash,256 bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89C52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning.The Power Down Mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next hardware reset.Pin Description：VCC ：Supply voltage.GND ：Ground.Port 0：Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs.Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pullups.Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pullups are required during program verification.Port 1：Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively.Port 2：Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verificationPort 3：Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also receives some control signals for Flash programming and programming verification.RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROGThis pin is also the program pulse input (PROG) during Flash programming.In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcrontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory. When the AT89C52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming when 12-volt programming is selected.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2：Output from the inverting oscillator amplifier.Special Function RegistersNote that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.Timer 2 Registers Control and status bits are contained in registers.T2CON and T2MOD for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.Data Memory：The AT89C52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space.When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space.For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2).MOV 0A0H, #data Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).MOV R0, #dataNote that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.Timer 0 and 1Timer 0 and Timer 1 in the AT89C52 operate the same way as Timer 0 and Timer 1 in the AT89C51.Timer 2：Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON.Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.In the Counter function, the register is incremented in response to a l-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.Capture Mode：In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a l-to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt.Auto-Reload (Up or Down Counter)Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Dow