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锁相技术译文翻译英文原文：AnOn-ChipAll-DigitalMeasurementCircuittoCharacterizePhase-LockedLoopResponsein45-nmSOI译文： 45纳米SOI全数字片上测量电路表征锁相环响应特性年级专业： 姓名： 学号： 2013 年 6 月 2 日英文中文AnOn-ChipAll-DigitalMeasurementCircuittoCharacterizePhase-LockedLoopResponsein45-nmSOIAbstractAnall-digitalmeasurementCircuit ,builtin45-nmSOI-CMOSenableson-chipcharacterizationofphase-lockedloop(PLL)responsetoaself-inducedphasestep. Thistechniqueallowsestimation ofPLLclosed-loopbandwidthandjitterpeaking.Thecircuitcan beusedtoplotstep-responsevs.time,measurestaticphaseerror, andobservephase-lockstatus.INTRODUCTIONManyapplicationssuchasPCIExpressrequireaPLLtoproducealow-jitterclockatagivenfrequencywhilemeetingstringentbandwidthandjitterpeakingrequirements.Process,voltage,andtemperature(PVT)variationsaswellasrandomdevicemismatchmakeitdifficulttoguaranteeanarrowrangeforPLLresponse.Forexample ,loopparameterssuchasVCOgain couldvarybymorethan2Xover PVTcorners.InFig.1,weseetheclosed-loopjittertransferfunctionsoftwoPLLswithidenticalreferenceclockandoutputfrequencies.OnePLLexhibitslargepeakingandlowbandwidthwhiletheothershowslittlepeakingbuthighbandwidth.Althoughdifferencesinthisexamplearemoreextremethanusual,similarbutsmallerdifferencesoftenresultfromPVTvariations. PLLresponseisoftenmeasuredonatestbenchusingsignalgenerators,oscilloscopes,and/orspectrumanalyzers.Forexample,thetransferfunctionsinFig.1wereautomaticallygeneratedbymodulatingthe100-MHzreferenceclockwithvariousfrequencieswhileobservingtheamplitudesoftheresultingoutputspurs.Suchmethods,whichmayrequiremanysecondstocomplete,motivatetheneedforfaster,lessexpensive,andpreferablyon-chiptechniquestocharacterizePLLresponse1-3.Fig.2showsthePLLoutputphasetransientresponsetoaninducedphasestep.Similartoothersecond-orderfeedbacksystems,thePLLtendstoovercorrect(orovershoot)asitworkstoeliminatetheinducedphaseerror.IfthePLLisunderdamped,asinthisexample,thePLLmayringseveraltimesbeforesettlingtoitsfinallockstate.AkeymetricinthePLLstep-responseiscrossover,definedhereasthe elapsedtimefrominputsteptoonsetofphaseovershoot.AnotherkeymetricisMaxOvershoot.It measuresthemaximumovercorrectioninthestepresponse.Transientsimulationsandclosed-formloopequations4showthatcrossoverisinverselyproportionaltothePLLs3dBclosed-loopbandwidth;thesmallercrossoveris,thehigherthebandwidth(Fig.3).Noticethatcrossoverislargelyindependentofthesizeofthephasestep.BothsimulationsandloopequationsalsopredictthatMaxOvershootisproportionaltothemaximumpeakingintheclosed-looptransferfunction;thelargerMaxOvershootis,thegreater thepeaking(Fig.4).Noticethatthemagnitudeoftheovershootisalsoproportionaltotheinputstepsize .Theserelationshipsbetweentime-andfrequency-domainbehaviorsallowustomakefasttime-domainmeasurementsandthenrelatetheresultsbacktofrequency-domainperformancespecifications. The circuit implementationpresentedinthispapershowsthatthePLLstepresponsemaybecapturedby anall-digital,on-chipfinitestatemachine,allowingforfastPLLcharacterization.SiliconresultsindicatethatthiscircuitcouldallowforPower-oncalibrationofthePLLbandwidthandpeakingforcompensationofprocessvariations.CIRCUITDESIGNThePLLundertest(Fig.5)isastandardinteger-Ncharge-pumpPLL.Theonlymodificationisthe additionofloopmeasurementcircuitry.Thefeedbackdivisor(N)isprogrammablefrom5to63，althoughN=8duringloopmeasurementtests.Thecharge-pumpcurrent,loop-filterresistance,andVCOgainareprogrammabletoallowforbandwidthandpeakingadjustmentsaswellasjitteroptimization.ThePLLbandwidthmaybeconfiguredfrom3to25MHzwhilethepeakingmaybevariedfrom4dB.TheVCOoperatesfrom1.6to5GHz.Theexpectedreferenceclockfrequency range is100to200MHz.Asimplewaytoinducethe requiredinputphasestepistoflipthepolarityofthereferenceclocksoitsphaseisadvancedbyhalfaclockcycle.Adisadvantagetothisapproachisthat themagnitudeofthephasestepisdependentonthereferenceclockdutycycle.Thisisundesirablebecauseovershoottestsrequire alargeandpredictableinputphasestep.Instead,thecircuitimplementationpresentedheremanipulatesthefeedbackdivisortoinduceaknownphasestep.Thecircuitthenautomaticallymeasuresthe resultingcrossoverandMaxOvershoot.Fig.6showsablockdiagram oftheloopmeasurementtestcircuit.Itincludesthreemainunits:control,crossoverdetector,andMaxOvershootdetector.Thecontrolunitcontainstwosynchronizers(toVCOclock),threeedgedetectors(risingandfalling),andlogic to enabletheinducedphasestep.Thecrossoverdetectorincludesabang-bangphasedetector,aphase-errorchange-of-signdetector,anda10-bitcounter.TheMaxOvershootdetectorcontainsafeedbackcountsampler,acomparator,andamaximumovershootregister. Thesestep-responsealgorithmsrequirethatthePLLstaticphaseerrorislessthanthemaximumovershoot.Ifnottrue,therequiredphaseerrorsign-changedoesnotoccur,thebandwidthcountersaturatesatitsmaximumvalue,andtheBwValidbitremainslow. Ifthestaticphaseerrorislarge,thentheFbClkphasecanbeadvanced,forcingaphaseerrorsign-change.Theresolutionofthe bandwidthtestisonereferenceclockperiod,andsothemeasurementbecomeslesspreciseasthePLLbandwidthApproachesthereferenceclock frequency.45纳米SOI全数字片上测量电路表征锁相环响应特性摘要-建立在45纳米的SOI-CMOS上一个全数字测量电路，它能够表征PLL对自诱导相步进的响应这项技术允许对PLL闭环带宽和抖动峰值的估计。这个电路被用来绘制阶跃响应随时间变化的曲线，测量静态相位误差和观察相位锁定状态。介绍很多应用例如PCIExpress需要一个PLL来产生一个低抖动的在一个给定频率的时钟，这个频率满足精确带宽和抖动峰值的要求。工艺，电压，和温度（PVT）变化以及随机的选择不搭配的器件都使得很难保证一个窄的变化范围的PLL响应，例如，环路参数如VCO增益变化可能超过PVT角2倍上以。图一中，我们可以看到两个具有相同参考时钟和输出频率PLL的闭环抖动传递函数一个PLL展现大的峰值和低带宽，而另一个展示了小峰值但是高带宽虽然这个例子中显示的差异比通常的要极端，这种相似会随着PVT的变化而变小PLL的响应往往使用一个信号发生器、示波器，和/或频谱分析仪。例如，在图一中传递函数是通过调制100MHz能产生各种频率的参考时钟同时观察输出马刺产生的幅值自动生成的。这种方法，可能需要一些时间去完成，这促进了更快，更便宜的方法的需要。比较好的方法是片上系统来表征PLL的响应特性1-3。表二表明致相步进响应的输出瞬态相位。类似于其他二阶反馈系统，PLL倾向于过调（或过调），那是因为它是为了消除相位误差。如果锁相环工作在欠阻尼状态，在这种状态下，PLL可能要经过几次锁存在达到最终锁存状态之前锁相环阶跃响应的一个关键指标是交叉反应。在此定义为从输入步进到相位超调开始出现所用的时间另一个关键指标是最大超调量。它可以测量阶跃响应的最大过调量。瞬态模拟和闭环回路方程4表明交叉反应和PLL的3dB闭环带宽成反比；交叉反应越小，带宽越大（图3）。请注意，交叉反应在很大程度上与相位步长无关。模拟和回路方程还预测到闭环传递函数中最大超调与最大峰值是成正比的;最大超调越大，峰值越高（图4）。请注意超调幅度也正比于输入步长。时域和频域的这种特性使得我们能够快速的时域测量然后关联到频域性能指标中去，电路实现显示：PLL阶跃响应可能被全数字化片上有限状态机捕获，从而实现快速表征锁相硅的实验效果表明，该电路可以让PLL带宽和峰值的电校准工艺变化得到弥补。电路设计被测PLL（图5）是一个标准的整数