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毕业设计
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USB接口波形发生器,毕业设计
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天津工程师范学院 2009 届 本科生 毕业设计 1 英文资料及 中文 翻译 PDIUSBD12-USB interface device with parallel bus The PDIUSBD12 is a cost and feature optimized USB device. It is normally used in microcontroller based systems and communicates with the system microcontroller over the high-speed general purpose parallel interface. It also supports local DMA transfer.This modular approach to implementing a USB interface allows the designer to choose the optimum system microcontroller from the available wide variety. This flexibility cuts down the development time, risks, and costs by allowing the use of the existing architecture and minimize firmware investments.This results in the fastest way to develop the most cost effective USB peripheral solution.The PDIUSBD12 fully conforms to the USB specification Rev. 2.0 (basic speed). It is also designed to be compliant with most device class specifications: Imaging Class, Mass Storage Devices, Communication Devices, Printing Devices, and Human Interface Devices.Assuch, the PDIUSBD 12 is ideally suited for many peripherals like Printer, Scanner, External Mass Storage (Zip Drive), Digital Still Camera, etc. It offers an immediate cost reduction for applications that currently use SCSI implementations.The PDIUSBD12 low suspend power consumption along with the Lazy Clock output allowsfor easy implementation of equipment that is compliant to the ACPI(TM),OnNOW(TM), and USB power management requirements. The low operating power allows the implementation of bus powered peripherals. In addition; it also incorporates features like SoftConnect(TM), GoodLink(TM), programmable clock output, low frequency crystal oscillator, and integration of termination resistors. All of these features contribute to significant cost savings in the system implementation and at the same time ease the implementation of advanced USB functionality into the peripherals. 1. DMA transfer Direct Memory Address (DMA) allows an efficient transfer of a block of data between thehostandlocalsharedmemory.UsingaDMAcontroller, data transfer between the PDIUSBD12s main endpoint (endpoint 2) and local shared memory can happen autonomously without local CPU intervention. Preceding any DMA transfer, the local CPU receives from the host the necessary setup information and programs the DMA controller accordingly. Typically, the DMA controller is set up for demand transfer mode and the byte count register and the address counter are programmed with the right values. In this mode, transfers occur only when the PDIUSBD12 requests them and are terminated when the byte count register reaches zero. After the DMA controller has been programmed, the DMA nts天津工程师范学院 2009 届 本科生 毕业设计 2 enable bit of the PDIUSBD12 is set by the local CPU to initiate the transfer. The PDIUSBD12 can be programmed for single-cycle DMA or burst mode DMA. In single-cycle DMA, the DMREQ pin is deactivated for every single acknowledgement by the DMACK_N before being re-asserted. In burst mode DMA, the DMREQ pin is kept active for the number of bursts programmed in the device before going inactive.This process continues until the PDIUSBD12 receives a DMA termination notice through pin EOT_N. This will generate an interrupt to notify the local CPU that DMA operation is completed. For DMA read operation,the DMREQ pin will only be activated whenever the buffer is full, signalling that the host has successfully transferred a packet to the PDIUSBD12.With the double buffering scheme, the host can start filling up the second buffer while the first buffer is being read out. This parallel processing increases the effective throughput.When the host does not fill up the buffer completely (lessthan64 bytesor 128 bytes for single direction ISO configuration), the DMREQ pin will be deactivatedat the last byte of the buffer regardless of the current DMA burst count. It will be re-asserted on the next packet with a refreshed DMA burst count. Similarly, for DMA write operations, the DMREQ pin remains active whenever the buffer is not full. When the buffer is filled up, the packet is sent over to the host on the next IN token and DMREQ will be reactivated if the transfer was successful. Also, the double buffering scheme here will improve throughput. For non-isochronous transfer (bulk and interrupt), the buffer needs to be completely filled up by the DMA writeoperation before the data is sent to the host. The only exception is at the end of DMA transfer, when the reception of pin EOT_N will stop DMA write operation and the buffer content will be sent to the host on the next IN token. For isochronous transfers, the local CPU and DMA controller have to guarantee that they are able to sink or source the maximum packet size in one USB frame (1 ms). The assertion of pin DMACK_Nautomatically selects the main endpoint (endpoint 2), regardless of the current selected endpoint. The DMA operation of the PDIUSBD12 can be interleaved with normal I/O access to other endpoints. DMA operation can be terminated by resetting the DMA enable register bit or the assertion of EOT_N together with DMACK_N and either RD_N or WR_N. The PDIUSBD12 supports DMA transfer in single address mode and it can also work in dual address mode of the DMA controller. In the single address mode, DMA transfer is done via the DREQ, DMACK_N, EOT_N, WR_N and RD_N control lines. In the dual address mode, pins DMREQ, DMACK_N and EOT_N are not used; instead CS_N, WR_N and RD_N control signals are used. The I/O mode Transfer Protocol of PDIUSBD12 needs to be followed. The source of the DMAC is accessed during the read cycle and the destination during the write cycle. Transfer needs to be done in two separate bus cycles, storing the data temporarily in the DMAC. Command description 2. Command procedure nts天津工程师范学院 2009 届 本科生 毕业设计 3 There are three basic types of commands: Initialization, Data Flow and General Commands. Respectively, these are used to initialize the function; for data flow between the function and the host; and some general commands. 2.1 Initialization commands Initialization commands are used during the enumeration process of the USB network. These commands are used to enable the function endpoints. They are also used to set the USB assigned address. Set Address/Enable Code (Hex):D0 Transaction: write 1 byte This command is used to set the USB assigned address and enable the function. Set endpoint enable Code (Hex):D8 Transaction: write 1 byte Thegeneric/Isochronous endpoints can only been abled when the function is enabled via the Set Address/Enable command. Set mode Code (Hex):F3 Transaction: write 2 bytes The Set mode command is followed by two data writes. The first byte contains the configuration bits. The second byte is the clock division factor byte. CLOCK DIVISION The value indicates the clock division factor for CLKOUT. The FACTOR output frequency is 48 MHz/(N+1) where N is the Clock Division Factor. The reset value is 11. This will produce the output frequency of 4 MHz which can then be programmed up or down by the user. The minimum value is 1 giving the range of frequency from 4 to 24 MHz. The minimum value of N is 0, giving a maximum frequency of 48 MHz.The maximum value of N is 11 giving a minimum frequency of 4 MHz.The PDIUSBD12 design ensures no glitching during frequency change. The programmed value will not be changed by a bus reset. Set DMA Code (Hex): FB Transaction: read/write 1 byte The set DMA command is followed by one data write/read to/from the DMA configuration register.DMA Configuration register: During DMA operation, the two-byte buffer header (status and byte length information) is not transferred to/from the local CPU. This allows DMA data to be continuous and not interleaved by chunks of this headers.For DMA read operations, the header will be skipped by the PDIUSBD12. For DMA write operations, the header will be automatically added by the PDIUSBD12. This provides for a clean and simple DMA data transfer. 2.2 Data flow commands Data flow commands are used to manage the data transmission between the USB endpoints and the external microcontroller. Much of the data flow is initiated via an nts天津工程师范学院 2009 届 本科生 毕业设计 4 interrupt to the microcontroller. The microcontroller utilizes these commands to access and determine whether the endpoint FIFOs have valid data. Read interrupt register Code (Hex):F4 Transaction: read 2 bytes This command indicates the origin of an interrupt. The endpoint interrupt bits (bits 0 to 5) are cleared by reading the endpoint last transaction status register through Read Last Transaction Status command. The other bits are cleared after reading the interrupt registers. Select Endpoint Code (Hex):00 to 05 Transaction: read 1 byte (optional) The Select Endpoint command initializes an internal pointer to the start of the selected buffer. Optionally, this command can be followed by a data read, which returns this byte. FULL/EMPTY: A 1 indicates the buffer is full, 0 indicates an empty buffer. STALL: A 1 indicates the selected endpoint is in the stall state. Fig 11. Select Endpoint command: bit allocation. Read Endpoint status Code (Hex):80 to 85 Transaction: read 1 byte Read last transaction status register Code (Hex):40 to 45 Transaction: read 1 byte The Read Last Transaction Status command is followed by one data read that returns the status of the last transaction of the endpoint. This command also resets the corresponding interrupt flag in the interrupt register, and clears the status, indicating that it was read.This command is useful for debugging purposes. Since it keeps track of every transaction, the status information is overwritten for each new transaction. Read buffer Code (Hex):F0 Transaction: read multiple bytes (max. 130) The Read Buffer command is followed by a number of data reads, which returns the contents of the selected endpoint data buffer. After each read, the internal buffer pointer is incremented by 1.The buffer pointer is not reset to the top of the buffer by the Read Buffer command.This means that reading or writing a buffer can be interrupted by any other command (except for Select Endpoint). The data in the buffer are organized as follows: * byte 0: reserved; can have any value * byte 1: number/length of data bytes * byte 2: data byte 1 * byte 3: data byte 2 * etc. The first two bytes will be skipped in the DMA read operation. Thus, the first read nts天津工程师范学院 2009 届 本科生 毕业设计 5 will get Data byte 1, the second read will get Data byte 2, etc. The PDIUSBD12 can determine the last byte of this packet through the EOP termination of the USB packet. Write buffer Code (Hex):F0 Transaction: write multiple bytes (max. 130) The Write Buffer command is followed by a number of data writes, which load the endpoints buffer. The data must be organized in the same way as described in the Read Buffer command. The first byte (reserved) should always be 0.During DMA writes operation, the first two bytes will be bypassed. Thus, the first write will write into Data byte 1, the second write will write into Data byte 2, etc. For non-isochronous transfer(bulk or interrupt), the buffer should be completely filled before the data is sent to the host and a switch to the next buffer occurs. The exception is at the end of DMA transfer indicated by activation of EOT_N, when the current buffer content (completely full or not) will be sent to the host. Remark: There is no protection against writing or reading over a buffers boundary or against writing into an OUT buffer or reading from an IN buffer. Any of these actions could cause an incorrect operation.Data in an OUT buffer are only meaningful after asuccessful transaction.The exception is during DMA operation on the main endpoint (endpoint 2), in which case the pointer is automatically pointed to the second buffer after reaching the boundary (double buffering scheme). Clear buffer Code (Hex):F2 Transaction: none When a packet is received completely, an internal endpoint buffer full flag is set. All Subsequent packets will be refused by returning a NAK.When the microcontroller has read the data, it should free the buffer by the Clear Buffer command. When the buffer is cleared, new packets will be accepted. Validate buffer Code (Hex): FA Transaction: none When the microprocessor has written data into an IN buffer, it should set the buffer full flag by the Validate Buffer command. This indicates that the data in the buffer are valid and can be sent to the host when the next IN token is received. Set endpoint status Code (Hex):40 to 45 Transaction: write 1 byte A stalled control endpoint is automatically unstalled when it receives a SETUP token, regardless of the content of the packet. If the endpoint should stay in its stalled state, the microcontroller can re-stall it.When a stalled endpoint is unstalled (either by the Set Endpoint Status command or by receiving a SETUP token), it is also re-initialized. This flushes the buffer and if it is an OUT buffer it waits for a DATA 0 PID, if it is an IN buffer it writes a DATA 0 PID.Even when unstalled, writing Set Endpoint Status to 0 initializes the endpoint. nts天津工程师范学院 2009 届 本科生 毕业设计 6 2.3 General commands Send resume Code (Hex)： F6 Transaction： none Sends an upstream resume signal for 10 ms.This command is normally issued when the device is in suspend. The RESUME command is not followed by a data read or write. Read current frame number Code (Hex)： F5 Transaction： read 1 or 2 bytes This command is followed by one or two data reads and returns the frame number of the last successfully received SOF. The frame number is returned Least Significant byte first. PDIUSBD12 带并行总线的 USB 接口器件 PDIUSBD12 是一款性价比很高的 USB 器件，它通常用作微控制器系统中实现与微控制器进行通信的高速 通用并行接口，它还支持本地的 DMA 传输。这种实现USB 接口的标准组件使得设计者可以在各种不同类型微控制器中选择出最合适的微控制器。这种灵活性减小了开发的时间，风险以及费用（通过使用已有的结构和减少固件上的投资），从而用最快捷的方法实现最经济的 USB 外设的解决方案。 PDIUSBD12 完全符合 USB1.1 版的规范，它还符合大多数器件的分类规格，成像类海量存储器件，通信器件，打印设备以及人机接口设备。同样地， PDIUSBD12理想地适用于许多外设。例如，打印机，扫描仪，外部的存储设备（ Zip 驱动器）和数码相机等等 。它使得当前使用 SCSI 的系统可以立即降低成本。 PDIUSBD12所具有的低挂起功耗连同 LazyClock 输出可以满足使用 ACPI， OnNOW 和 USB 电源管理的要求，低的操作功耗可以应用于使用总线供电的外设。此外它还集成了许多特性，包括 SoftConnetTM， GoodLinkTM， 可编程时钟输出，低频晶振和终止寄存器集合。所有这些特性都为系统显著节约了成本，同时使 USB 功能在外设上的应用变得容易。 1. DMA 传输 直接存储器寻址 （ DMA）允许在主端点和本地共享存储器间实现数据块的有效传输。使用 DMA 控制器， PDIUSBD12 的主端点和本地共享存储器间的数据传输可自主进行而不需要本地 CPU 的干预。要处理任何 DMA 传输，本地 CPU 从主机接收必要的 SETUP 信息并对 DMA 控制器进行相应的编程，典型的对 DMA 控制器的nts天津工程师范学院 2009 届 本科生 毕业设计 7 传输模式，字节计数寄存器和地址计数器进行正确的编程。在该模式下，PDIUSBD12 发出请求时开始传输。当字节计数器减少为零时终止。在 DMA 控制器编程之后，本地 CPU 在初始化传输时将 PDIUSBD12 中的 DMA 使能位置位。 PDIUSBD12 可编程为单周期 DMA 或突发模式 DMA。在单周期 DMA 中， DMREQ在每单个应答后直到被 DMACK_N 重新激活之前保持无效。在突发模式 DMA 中，DMREQ 在器件中突发编程时一直保持有效。该过程持续到 PDIUSBD12 通过 EOT_N接收到一个 DMA 终止信息。这时产生一个中断指示本地 CPU DMA 操作已经完成。 在 DMA读操作时 DMREQ仅当缓冲区完全表示主机成功的发送了一个信息包到PDIUSBD12 时才有效。由于具有双缓冲配置，主机可以在第一个缓冲区被读出时对第二个缓冲区进行填充，这种并行的处理 有效的增加了数据吞吐量。当主机没有完全填满缓冲区的情况下（单向 ISO 配置时小于 64 或 128 字节）， DMREQ 会在缓冲区的最后一个字节时无效 而不管当前的 DMA 突发计数。在更新了 DMA 突发计数的下一个包发送时， DMREQ 再次被激活。 DMA 的写操作与之相似，当缓冲区未装满时， DMREQ 一直有效。当缓冲区填满时，在下一个 IN 标志将信息包送入主机。当传输完成之后， DMREQ 变为无效。同样的，双缓冲配置在这也改善了数据的吞吐量。在非同步传输中，批量模式和中断。在数据被发送到主机之前，缓冲区需要通过 DMA 写操作完全装 满。唯一的例外是，在 DMA 传输结束时， EOT_N 接收的信号将会停止 DMA 写操作并且在下一个 IN 标志置位时将缓冲区的内容传送到主机。 在同步模式中，本地 CPU 和 DMA 控制器必须保证它们在一个 USB 帧（ 1ms）中能够吞吐的最大信息包的规模。 DMACK_N 的激活将自动选择主端点（端点 2）而不管当前选择的端点。 PDIUSBD12 的 DMA 操作可通过普通的 I/O 对其它端点的存取实现交叉存取。 DMA 操作可通过以下方式终止：复位 DMA 使能寄存器位或EOT_N 加上 DMACK_N 以及 RD_N/WR_N 的激活。 PDIUSBD12 支持单地址模式中的 DMA 传输，也可以在 DMA 控制器的双地址模式中工作。在单地址模式中 DMA 通过 DREQ DMACK_N,EOT_N,WR_N 和 RD_N 控制线实现传输。在双地址模式中 DMREQ,DMACK_N 和 EOT_N 未用，取而代之的是CS_N,WR_N 和 RD_N 控制信号。需要遵循 PDIUSBD12 的 I/O 模式传输协议。在读周期中对 DMAC 信号源进行访问，在写周期对目标进行访问，传输需要两个单独的总线周期来储存暂存在 DMAC 中的数据。 2. 命令描述 有 3 种基本的类型的命令：初始化，数据流和通用命令。 2.1 初始化命令 初始化命令在 USB 网络进行枚举处理时使用，这些命令用于使能端点的功能，还可用来设置 USB 配的地址。 设置地址 /使能 命令： D0h 处理：写 1 字节 该命令用于设置 USB 分配的地址和使能功能。 nts天津工程师范学院 2009 届 本科生 毕业设计 8 地址 写入的值即为地址 使能 置 1 使能该功能 设置端点使能 命令： D8h 处理：写 1 字节 通过设置设置地址 /使能命令后才可使能普通 /同步端点 普通 /同步 端点 值 1 表示普通 /同步端点使能 设置模式 命令： F3h 处理：写 2 字节 设置模式命令后跟 2 个写入的数据，第一个字节包含配置字节信息，第二个字节是时钟分频因素字节。 配置字节 无 LazyClock： 1 表示 CLKOUT 不会切换到 LazyClock， 0 表示 CLKOUT 在 Suspend脚变高之后切换到 LazyClock， LazyClock 频率是 30KHz 40%，编程值将不过会被总线复位所改变。 时钟运行： 1 表示内部时钟和 PLL 即使在挂起状态下仍然运行， 0 表示只要不需要时，内部时钟晶振和 PLL 就停止运行， 为了满足严格的挂起电流要求，该位需要设置为 0，已编程的值不会被总线复位所改变。 中断模式： 1 表示报告所有的错误和“ NAKing”并产生一个中断。 0 表示只有 OK被报告。编程值不会被总线复位所改变。 SoftConnect： 1 表示如果 VBUS 可用，上行数据上拉电阻就被连接， 0 表示不连接。已编程的值不会被总线复位所改变。 端点配置：该 2 位设置端点配置如下： 模式 0 非同步模式 模式 1 同步输出模式 模式 2 同步输入模式 模式 3 同步输入 /输出模式 时钟分频系数字节 时钟分频系数：该值用来表示 CLKOUT 的时钟分频系数，用 N 表示分频系数，那么输出频率就为 48MHz/(N+1)，复位值为 11。这产生 4MHz 的输出频率，然后可由用户自行调节。当 N 为 0 时，得到最大频率 48MHz，当 N 取最大 11 时，得到最小频率 4MHz。 PDIUSBD12 的设计确保了在改变频率时不会出现干扰，已编程的值不会被总线复位所改变。 SET_TO_ONE：该位需要在任何 DMA 读或写操作之前置为 1。该位在上电复位值为0。复位后可将其一直设为 1。 仅有 SOF 中断模式：将该位置 1 后 ，仅当帧时钟的起始（ SOF）时刻引起中断的产生 而不管引脚中断模式的设置状态设置（ DMA 位 5） 设置 DMA 命令： FBh 处理：读 /写 1 字节 设置 DMA 命令后跟 1 个字节数据写入 /读出 DMA 配置寄存器 nts天津工程师范学院 2009 届 本科生 毕业设计 9 DMA 配置寄存器 在 DMA 操作中，两字节的缓冲区头（状态和字节长度信息）不参与传送。这就允许了 DMA 数据的连续性，不插入信息头。 DMA 读操作时，信息头被 PDIUSBD12 跳过，在 DMA 写操作时，信息头由 PDIUSBD12 自动添加，这就提供了一个简洁的DMA 数据传输。 DMA 突发串：选择 DMA 操作的突发串长度 00 单周期 DMA 01 突发串 4 周期 DMA 10 突发串 8 周期 DMA 11 突发串 16 周期 DMA DMA 使能：向该位写入 1 会通过激活 DMREQ 启动 DMA 操作，在激活 DMREQ 之前需要装满（ DMA 读操作）或清空（ DMA 写操作）主端点缓冲区。在单周期 DMA 模式中， DMREQ 在突发串数目耗尽后无效，然后下一个突发串时重新激活，这个过程一直持续到 EOT_N 和 DMACK_N 以及 RD_N 或 WR_N 一起被激活。此时将该位置 0并终止 DMA 操作， DMA 操作也可通过直接向该位写入 0 来终止。 DMA 方向：该位决定了 DMA 传输时数据流的方向， 1 表示从外部共享存储器到PDIUSBD12（ DMA 写操作）， 0 表示从 PDIUSBD12 到外部共享存储器（ DMA 读操作）。 自动重装：当该位设为 1， DMA 操作会自动重新启动。 中断脚模式： 0 表示正常的中断脚模式，中断寄存器所有位的逻辑或产生中断，当该位写入 1 时表示中断会在 USB 总线上行数据流出现帧时钟（ SOF）起始位时产生中断。其它中断仍然有效。 端点索引 4 中断使能：该位为 1 表示只要端点缓冲区包含一个有效的信息包 就会产生中断，通常在 DMA 操作时关闭以减少不必要的 CPU响应。 端点索引 5 中断使能：该位为 1 表示只要端点缓冲区有效，见缓冲区生效命令，就会产生中断，通常在 DMA 操作时关闭以减少不必要的CPU 响应。 2.2 数据流命令 数据
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