EDA基于VHDL的乐曲播放电路设计报告.doc

乐曲播放电路设计乐曲播放电路顶层电路图二、模块和源程序1、分频模块分频顶层电路library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity yourname_div isport(clk50mhz:in std_logic; clk5mhz:buffer std_logic; clk1khz:out std_logic); end entity;architecture behav of yourname_div issignal clk50khz:std_logic;begin process(clk50mhz)variable cnt:integer range 0 to 9;beginif(clk50mhzevent and clk50mhz=1) thenif cnt9 then cnt:=cnt+1;clk5mhz=0;else cnt:=0;clk5mhz=1;end if;end if;end process;process(clk5mhz)variable cnt1:integer range 0 to 99;beginif(clk5mhzevent and clk5mhz=1) then if cnt199 then cnt1:=cnt1+1;clk50khz=0;else cnt1:=0;clk50khz=1;end if;end if;end process;process(clk50khz)variable cnt2:integer range 0 to 49;beginif(clk50khzevent and clk50khz=1) then if cnt249 then cnt2:=cnt2+1;clk1khz=0;else cnt2:=0;clk1khz=1;end if;end if;end process;end behav;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity yourname_div2 isport(clk:in std_logic; q:out std_logic);end yourname_div2;architecture rtl of yourname_div2 isbegin process(clk) variable cnt:std_logic_vector(0 downto 0); begin if clkevent and clk=1 then if cnt0); end if; end if; if cnt=1 then q=1; else q=0; end if; end process;end rtl;2、music_tone 模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity yournamemusic_tone isport(cs:in std_logic; index:in std_logic_vector(3 downto 0); code:out std_logic_vector(3 downto 0); high:out std_logic_vector(3 downto 0); tone:out std_logic_vector(10 downto 0);end entity;architecture one of yournamemusic_tone issignal index1:integer range 0 to 15;signal tone1:integer range 0 to 2047;signal code1:integer range 0 to 15;beginindex1=conv_integer(index);tone=conv_std_logic_vector(tone1,11);codetone1=2047;code1=0;hightone1=773;code1=1;hightone1=912;code1=2;hightone1=1036;code1=3;hightone1=1092;code1=4;hightone1=1197;code1=5;hightone1=1290;code1=6;hightone1=1372;code1=7;hightone1=1410;code1=1;hightone1=1480;code1=2;hightone1=1542;code1=3;hightone1=1570;code1=4;hightone1=1622;code1=5;hightone1=1669;code1=6;hightone1=1710;code1=7;hightone1=1729;code1=1;highnull; end case;else case index1 is when 0=tone1=2047;code1=0;hightone1=137;code1=1;hightone1=345;code1=2;hightone1=531;code1=3;hightone1=616;code1=4;hightone1=772;code1=5;hightone1=912;code1=6;hightone1=1036;code1=7;hightone1=1092;code1=1;hightone1=1197;code1=2;hightone1=1290;code1=3;hightone1=1332;code1=4;hightone1=1410;code1=5;hightone1=1480;code1=6;hightone1=1542;code1=7;hightone1=1570;code1=1;highnull; end case;end if;end process;end one;3、music_rom模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity yourname_music_rom is port (clk:in std_logic;stop:in std_logic;nextone:in std_logic;replay:in std_logic;xianshi:out std_logic_vector(3 downto 0);index:out std_logic_vector(3 downto 0);end yourname_music_rom;architecture behav of yourname_music_rom issubtype word is integer range 0 to 15;type memory is array (0 to 495) of word;signal rom:memory;signal clk_cnt:integer range 0 to 249;signal clk_4hz:std_logic;signal adr:integer range 0 to 495;begin divide: process(clk)begin if clkevent and clk=1 then if clk_cnt=249 then clk_cnt=0; clk_4hz=1;else clk_cnt=clk_cnt+1; clk_4hz=0 and adr=112 then adr=113 and adr=248 then adr=249 and adr=495 then adr=249; -disanshaouge end if; elsif replay=1 and stop=0 and nextone=1 then adr=0 and adr=112 then adr=113 and adr=248 then adr=249 and adr=495 then adr=0; end if; elsif replay=1 and stop=1 and nextone=1 then if adr=495 then adr=0; else adr=0 and adr=112 then xianshi=113 and adr=248 then xianshi=248 and adr=495 then xianshi=0011; end if; end if;end process;process(stop)begin if stop=0 thenindex=0000;else index=conv_std_logic_vector(rom(adr),4); rom(0)=10;rom(1)=10;rom(2)=10;rom(3)=10; rom(4)=11;rom(5)=11;rom(6)=12;rom(7)=12; rom(8)=12;rom(9)=12;rom(10)=11;rom(11)=11; rom(12)=10;rom(13)=10;rom(14)=9;rom(15)=9; rom(16)=8;rom(17)=8;rom(18)=8;rom(19)=8; rom(20)=9;rom(21)=10;rom(22)=10;rom(23)=10; rom(24)=10;rom(25)=10;rom(26)=10;rom(27)=9; rom(28)=9;rom(29)=9;rom(30)=9;rom(31)=9; rom(32)=10;rom(33)=10;rom(34)=10;rom(35)=10; rom(36)=11;rom(37)=11;rom(38)=12;rom(39)=12; rom(40)=12;rom(41)=12;rom(42)=11;rom(43)=11; rom(44)=10;rom(45)=10;rom(46)=9;rom(47)=9; rom(48)=9;rom(49)=8;rom(50)=9;rom(51)=9; rom(52)=10;rom(53)=10;rom(54)=9;rom(55)=9; rom(56)=9;rom(57)=8;rom(58)=8;rom(59)=8; rom(60)=8;rom(61)=8;rom(62)=9;rom(63)=9; rom(64)=9;rom(65)=9;rom(66)=10;rom(67)=10; rom(68)=8;rom(69)=8;rom(70)=9;rom(71)=9; rom(72)=10;rom(73)=11;rom(74)=10;rom(75)=10; rom(76)=8;rom(78)=9;rom(79)=5;rom(80)=5; rom(81)=10;rom(82)=10; rom(83)=10;rom(84)=10;rom(85)=10;rom(86)=10; rom(87)=11;rom(88)=11;rom(89)=12;rom(90)=12; rom(91)=12;rom(92)=12;rom(93)=11;rom(94)=11; rom(95)=10;rom(96)=10;rom(97)=11;rom(98)=9; rom(99)=8;rom(100)=8;rom(101)=8;rom(102)=8; rom(103)=9;rom(104)=9;rom(105)=10;rom(106)=10; rom(107)=9;rom(108)=9;rom(109)=9;rom(110)=8; rom(111)=8;rom(112)=8; rom(113)=3;rom(114)=3; rom(115)=5;rom(116)=5;rom(117)=5;rom(118)=6; rom(119)=8;rom(120)=8;rom(121)=8;rom(122)=9; rom(123)=6;rom(124)=8;rom(125)=5;rom(126)=5; rom(127)=12;rom(128)=15;rom(129)=13;rom(130)=12; rom(131)=10;rom(132)=12;rom(133)=9;rom(134)=2; rom(135)=10;rom(136)=10;rom(137)=7;rom(138)=6; rom(139)=5;rom(140)=5;rom(141)=6;rom(142)=8; rom(143)=9;rom(144)=3;rom(145)=3;rom(146)=5; rom(254)=5;rom(147)=6;rom(148)=5;rom(149)=5; rom(150)=6;rom(151)=8;rom(152)=8;rom(153)=5; rom(154)=10;rom(155)=10;rom(156)=7; rom(157)=7;rom(158)=9;rom(159)=6;rom(160)=8; rom(161)=5;rom(162)=5;rom(163)=3;rom(164)=5; rom(165)=3;rom(166)=5;rom(167)=6;rom(168)=7; rom(169)=9;rom(170)=6;rom(171)=6;rom(172)=0; rom(173)=5;rom(174)=6;rom(175)=8;rom(176)=9; rom(177)=12;rom(178)=10;rom(179)=9;rom(180)=9; rom(181)=10;rom(182)=9;rom(183)=8;rom(184)=6; rom(185)=6;rom(186)=5;rom(187)=3;rom(188)=3; rom(189)=10;rom(190)=6;rom(191)=5;rom(192)=6; rom(193)=8;rom(194)=5;rom(195)=3;rom(196)=3; rom(197)=5;rom(198)=5;rom(199)=6;rom(200)=8; rom(201)=8;rom(202)=9;rom(203)=6;rom(204)=8; rom(205)=5;rom(206)=5;rom(207)=12;rom(208)=15; rom(209)=13;rom(210)=12;rom(211)=10;rom(212)=12; rom(213)=9;rom(214)=9;rom(215)=9;rom(216)=10; rom(217)=7;rom(218)=6;rom(219)=5;rom(220)=6; rom(221)=8;rom(222)=9;rom(223)=3;rom(224)=3; rom(225)=5;rom(226)=5;rom(227)=5;rom(228)=6; rom(229)=5;rom(230)=6;rom(231)=8;rom(232)=5; rom(233)=6;rom(234)=6;rom(235)=6;rom(236)=7; rom(237)=8;rom(238)=8;rom(239)=8;rom(240)=6; rom(241)=8;rom(242)=8;rom(243)=7;rom(244)=6; rom(245)=7;rom(246)=7;rom(247)=3;rom(248)=0; rom(249)=12;rom(250)=12;rom(251)=14;rom(252)=13;rom(253)=13;rom(255)=13;rom(256)=12;rom(257)=13;rom(258)=13;rom(259)=15;rom(260)=15;rom(261)=15;rom(262)=14;rom(263)=12;rom(264)=13;rom(265)=13;rom(266)=13;rom(267)=13;rom(268)=12;rom(269)=13;rom(270)=12;rom(271)=10;rom(272)=12;rom(273)=12;rom(274)=12;rom(275)=12;rom(276)=12;rom(277)=14;rom(278)=13;rom(279)=13;rom(280)=13;rom(281)=13;rom(282)=12;rom(283)=13;rom(284)=13;rom(285)=13;rom(286)=13;rom(287)=15;rom(288)=14;rom(289)=15;rom(290)=14;rom(291)=13;rom(292)=15;rom(293)=14;rom(294)=15;rom(295)=14;rom(296)=13;rom(297)=0;rom(298)=14;rom(299)=13;rom(300)=12;rom(301)=10;rom(302)=12;rom(303)=13;rom(304)=13;end if;end process;end behav;4、music_speaker模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity yourname_music_speaker isport(clk:in std_logic;tone:in std_logic_vector(10 downto 0);spks: out std_logic);end yourname_music_speaker;architecture one of yourname_music_speaker issignal preclk: std_logic;signal Fullspks:std_logic;signal tonel:integer range 0 to 16#7ff#;begin tonel=conv_integer(tone);divideclk:process(clk)variable count4:integer range 0 to 100;begin preclk=5 thenpreclk=1;count4:=0;elsif clkevent and clk=1thencount4:=count4+1;end if;end process;genspks:process(preclk,tonel)variable count11:integer range 0 to 16#7ff#;begin if preclkevent and preclk=1 thenif count11= 16#7ff#thencount11:=tonel;fullspks=1;else count11:=count11+1;fullspks=0;end if;end if;end process;delayspks:process(fullspks)variable count2:std_logic;begin if fullspksevent and fullspks=1thencount2:=not count2;if count2=1thenspks=1;else spks=0;end if; end if;end process;end one;5、数码管动态扫描显示模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity yourname_music_display isport(din0:in std_logic_vector(3 downto 0); din1:in std_logic_vector(3 downto 0); din2:in std_logic_vector(3 downto 0); din3:in std_logic_vector(3 downto 0); din4:in std_logic_vector(3 downto 0); din5:in std_logic_vector(3 downto 0); clk:in std_logic; LED_SA:out std_logic; LED_SB:out std_logic; LED_SC:out std_logic; LED_A:out std_logic; LED_B:out std_logic; LED_C:out std_logic; LED_D:out std_logic; LED_E:out std_logic; LED_F:out std_logic; LED_G:out std_logic; LED_DP:out std_logic);end yourname_music_display;architecture behave of yourname_music_display issignal seg:std_logic_vector(6 downto 0);signal sel:std_logic_vector(2 downto 0);signal num:std_logic_vector(3 downto 0);signal s:std_logic_vector(2 downto 0);beg