CPU VHDL代码及详细注释.doc

一个TISC的模拟cpu代码，一共有200多行，不过麻雀虽小，却五脏俱全，而且作者对每行代码都做了详细的说明，下面仔细的分析一下。先看看作者写的指令说明：- Vins VHDL Tisc CPU Core, 15th Nov 2001- My first attempt at processor design, thanks to :- Tim Boscke - CPU8BIT2, Rockwell - 6502, Microchip - Pic- Jien Chung Lo - EL405 , Steve Scott - Tisc,- Giovanni Moretti - Intro to Asm- Uses 12 bit program word, and 8 bit data memory- 2 reg machine,accumulator based, with akku and index regs- Harvard architecture, uses return x so as to eliminate need of pmem- indirect instructions like 8051.- pc is 10 bits, akku and idx are 8 bit.- Has carry and zero flags,- three addressing modes:- immediate, indirect and reg.- seperate program and data memory for pipelining later.- Instructions coded as thus:- Long instructions first - program jump.- Both store return address for subroutine calls, 1 deep stack.- 0 0 xxxxxxxxxx jcpmem10 ; if c=1, stack = pc, pc - pmem10, fi- 0 1 xxxxxxxxxx jz pmem10 ; if z=1, stack = pc, pc 如果为1则进行取数运算及准备aluop,并设定目标akku转换到状态000,指令译码操作。 if( states(2) = 1) then if( states(1 downto 0) = 01) then -sub add ind temp = 0 & (Not data(7 downto 0); else temp = 0 & data(7 downto 0); end if; aluop = states(1 downto 0); - 00 adc indirect - 01 not add ind - 10 and indirect - 11 nor indirect - sort out muxers for alu aludest = 00; - akku destination states - destination is alu akku - alu destination is idx idx null; end case; - end of dest decode（3）alu运算 两个并发运算过程,确定aluinput及aluout。 - alu input muxer with aludest select aluinput = (0 & akku) when 00, (00 & idx) when 11, pc when 10, (0 & temp) when others; - Decode and perform arithmetic ops with aluop select aluout = aluinput + (0 & temp) when 01, - add aluinput and (0 & temp) when 10, - and aluinput nor (0 & temp) when 11, - nor not (0 & temp) when others; - any use?（4）由于states - instruction decode - increment pc first temp = 000000001; - inc aludest = 10; - pc and increment and idle pc = aluout; - get result 这里似乎缺少 aluop = 00 运算。 主要作用：PC指针加1 （5）地址，数据及读写信号的输出 -状态变化时触发- assign pins address = pc when states = 000 else 00&idx; data = (000 & akku) when states = 011 else ZZZZZZZZZZZZ; psen = 0 when states=000 else 1;- pmem read rd = 0 when (states(2)=1) or (states=010) else 1; - dmem read wr= 0 when states=011 else 1;- dmem write4 详细代码清单- Vins VHDL Tisc CPU Core, 15th Nov 2001- My first attempt at processor design, thanks to :- Tim Boscke - CPU8BIT2, Rockwell - 6502, Microchip - Pic- Jien Chung Lo - EL405 , Steve Scott - Tisc,- Giovanni Moretti - Intro to Asm- Uses 12 bit program word, and 8 bit data memory- 2 reg machine,accumulator based, with akku and index regs- Harvard architecture, uses return x so as to eliminate need of pmem- indirect instructions like 8051.- pc is 10 bits, akku and idx are 8 bit.- Has carry and zero flags,- three addressing modes:- immediate, indirect and reg.- seperate program and data memory for pipelining later.- Instructions coded as thus:- Long instructions first - program jump.- Both store return address for subroutine calls, 1 deep stack.- 0 0 xxxxxxxxxx jcpmem10 ; if c=1, stack = pc, pc - pmem10, fi- 0 1 xxxxxxxxxx jz pmem10 ; if z=1, stack = pc, pc - pmem10, fi- Immediate ops- bits 9 and 8 select what to do- 1 00 0 xxxxxxxx lda #imm8 ; a= imm8, c=0,- 1 00 1 xxxxxxxx ret #imm8 ; a= imm8, pc = stack- 1 01 0 xxxxxxxx adc #imm8 ; add with carry imm8, cy and z set- 1 01 1 xxxxxxxx adx #imm8 ; add imm8 to idx reg, z=(a=0)- Indirect and alu ops- bit 9 selects indirect or alu ops- Indirect - bits 7 and 8 select what to do- 1 10 0 0xxxxxxx lda ix ; load a indirect data mem- 1 10 0 1xxxxxxx sta ix ; store a indirect data mem- register register- 1 10 1 0xxxxxxx tax ; x = a,- 1 10 1 1xxxxxxx txa ; a = x- Arithmetic ops use indirect addressing- all alu ops indirect, bits 7 and 8 select alu op.- 1 11 00xxxxxxx add a,ix; add with carry- 1 11 01xxxxxxx sub a,ix; a = a + idx, inc a after for proper subtract- 1 11 10xxxxxxx and a,ix; and mem contents into a- 1 11 11xxxxxxx nor a,ix; nor- States. - 000instruction decode - 010load a indirect - lda ix- 011stor a indirect - sta ix- 100add a,ix - 101sub a,ix- 110and a,ix- 111nor a,ixlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all; - has adder built inentity tisc is port( - bus - db only 8 bits wide on dmem side, 12 on pmem side. data : inout std_logic_vector(11 downto 0); address : out std_logic_vector(9 downto 0); - control - active low rd : out std_logic; - dram wr : out std_logic; - dram psen : out std_logic;- pmem - machine control clock : instd_logic; reset : instd_logic);end;architecture cpu_arch of tisc is - Program control signal stack : std_logic_vector(9 downto 0); - stack, 1 deep signalpc : std_logic_vector(9 downto 0); - program counter - Registers signalakku : std_logic_vector(8 downto 0); - accumulator, cy is bit 8 signalidx : std_logic_vector(7 downto 0); - index reg signalz : std_logic; - zero flag - ALU controls signalaluout : std_logic_vector(9 downto 0); - alu result signaltemp : std_logic_vector(8 downto 0); - temp storage for alu signalaludest : std_logic_vector(1 downto 0); - output mux alu signalaluop : std_logic_vector(1 downto 0); - alu operation signalaluinput : std_logic_vector(9 downto 0); - input to alu - machine control signal states : std_logic_vector(2 downto 0); - state controllerbegin - start logic declerationprocess(clock,reset) - sequential sectionbegin - check if reset or not if(reset = 0 ) then - async reset parameters - how do I stop the annoying async error? pc 0);- reset states 0); - decode sub state aludest= 01; - reset destination dest elsif rising_edge(clock) then -actual machine - check state machine for indirect alu ops if( states(2) = 1) then if( states(1 downto 0) = 01) then -sub add ind temp = 0 & (Not data(7 downto 0); else temp = 0 & data(7 downto 0); end if; aluop = states(1 downto 0); - 00 adc indirect - 01 not add ind - 10 and indirect - 11 nor indirect - sort out muxers for alu aludest = 00; - akku destination states - instruction decode - increment pc first temp = 000000001; - inc aludest = 10; - pc and increment and idle pc = aluout; - get result - Now decode instr on data bus - sort out jz or jc if( (data(11) = 0) and - top bit nought, sio a jump. ( (akku(8) = 1) and (data(10) = 0) or - JC (z=1) and (data(10)=1) ) then - Jz stack = pc; -return stack pc - adc #imm/adx #imm temp = 0 & data(7 downto 0); aluop = 01; - add aludest - lda #imm/ret #imm clear cy if( data(8) = 1 ) then - ret #imm pc = stack; end if; akku - lda/store or reg/reg if( data(8) = 1) then - ld ind /store ind states = 01 & data(7);- 010; - reg/reg elsif( data(7) = 0) then- tax idx = akku(7 downto 0); else - txa akku - add ind, and states states - lda ix - buses should be setup akku = 0 & data(7 downto 0); states - sta ix - akku placed on data bus now states states - destination is alu akku - alu destination is idx idx null; end case; - e