数字系统仿真与VHDL课程设计报告.doc

数字系统仿真与VHDL课程设计报告学院：信息与电气工程学院专业：通信工程班级：通信一班姓名：李世辉学号：0804040102指导老师：张剑 胡仕刚设计时间：2010.1.32010.1.14 目录1 课程设计任务2 课程设计目的3 课程设计的基本要求4 设计流程图5 Max+plus II设计软件的基本操作6 课程设计内容七课程设计心得体会一课程设计的任务1.本次设计的任务是熟悉支持VHDL语言的软件，例如：MAXPLUS2，ISP，FOUNDATION等，利用这一类软件使用VHDL语言进行设计。二课程设计目的1. 熟练掌握相关软件的使用，操作。能对VHDL语言程序进行编译，调试，以及通过计算机仿真，得到正确的仿真波形图，并根据所得仿真波形图分析判断并改进所设计的电路。2. 在成功掌握软件操作基础上，将所学数字电路的基础课知识与VHDL语言的应用型知识结合起来并与实际设计，操作联系起来，即“理论联系实际”。3. 深入了解VHDL语言的作用与价值，对用硬件语言设计一个电路系统开始具备一个较完整的思路与较专业的经验。对EDA技术有初步的认识，并开始对EDA技术的开发创新有初步的理解。三设计的基本要求 1.熟悉数字电路及相关专业课程的基本知识并能联系具体程序 2.正确操作使用VHDL语言相关软件，能编译，调试，仿真VHDL 语言程序 3.设计数字电路，编写程序，实现电路功能。四. 设计流程图 五Max+plus II设计软件的基本操作 1.设计输入 原理图设计输入法 文本设计输入法 波形输入法 层次化设计输入法 2.项目编译 语法检查和设计规则检查 设计综合 生成编程数据文件 3.仿真和定时分析 仿真(Simulation) 定时分析(Timing Analysis) 4.编程下载，调试与仿真 5.波形图的分析六课程设计内容 1.设计60进计数器设计一个BCD码60进计数器。要求实现同步，异步两种情况，且规定个位显示09，十位显示05，均用4位二进制数表示。在此基础上试用VHDL语言描述中小规模集成电路74LS169。(1) .60进制同步计数器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY count60tb ISPORT(clk,w1c,w2c,cin:IN STD_LOGIC; cout:OUT STD_LOGIC; data_in:IN STD_LOGIC_VECTOR(3 DOWNTO 0); ge:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); shi:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END ENTITY count60tb;ARCHITECTURE example OF count60tb ISSIGNAL ge_n:STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL shi_n:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINge=ge_n;shi=shi_n;PROCESS(clk,w1c) ISBEGINIF(W1C=1) THENge_n=data_in(3 DOWNTO 0);ELSIF(clkEVENT AND clk=1) THENIF(cin=1) THEN IF(ge_n=9) THENge_n=0000;ELSEge_n=ge_n+1;END IF;END IF;END IF;END PROCESS;PROCESS(clk,w2c) ISBEGINIF(w2c=1) THENshi_n=data_in(3 DOWNTO 0);ELSIF(clkEVENT AND clk=1) THENIF(cin=1 AND ge_n=9) THENIF(shi_n=5) THENshi_n=0000;ELSEshi_n=shi_n+1;END IF;END IF;END IF;END PROCESS;PROCESS(clk,ge_n,shi_n) ISBEGINIF(clkEVENT AND clk=1 )THENIF(ge_n=9 AND shi_n=5 AND cin=1) THENcout=1;ELSEcout=0;END IF;END IF;END PROCESS;END ARCHITECTURE example;(2) 60进制异步计数器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY count60yb ISPORT(clk,w1c,w2c,cin1:IN STD_LOGIC; cout2:OUT STD_LOGIC; data_in:IN STD_LOGIC_VECTOR(3 DOWNTO 0); ge:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); shi:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END ENTITY count60yb;ARCHITECTURE example OF count60yb ISSIGNAL ge_n:STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL shi_n:STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL cin2,cout1:STD_LOGIC;BEGINge=ge_n;shi=shi_n;cin2=cout1;PROCESS(clk,w1c) ISBEGINIF(W1C=1) THENge_n=data_in(3 DOWNTO 0);ELSIF(clkEVENT AND clk=1) THENIF(cin1=1) THEN IF(ge_n=9) THENge_n=0000;ELSEge_n=ge_n+1;END IF;END IF;END IF;END PROCESS;PROCESS(cin2) ISBEGINIF(w2c=1) THENshi_n=data_in(3 DOWNTO 0);ELSEIF(cin2=1) THENIF(shi_n=5) THENshi_n=0000;ELSEshi_n=shi_n+1;END IF;END IF;END IF;END PROCESS;PROCESS(clk,ge_n,shi_n) ISBEGINIF(clkEVENT AND clk=1 )THENIF(ge_n=9 AND cin1=1) THENcout1=1;ELSEcout1=0;END IF;IF(shi_n=5 AND cin2=1) THENcout2=1;ELSEcout2=0;END IF;END IF;END PROCESS;END ARCHITECTURE example;(3) 74LS169模块LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ls169 ISPORT(clk,wr,sel,cin:IN STD_LOGIC; cout:OUT STD_LOGIC; data_in:IN STD_LOGIC_VECTOR(3 DOWNTO 0);data_out:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END ENTITY ls169;ARCHITECTURE example OF ls169 ISSIGNAL data:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINdata_out=data;PROCESS(clk,wr) ISBEGINIF(wr=1) THENdata=data_in(3 DOWNTO 0);ELSIF(clkEVENT AND clk=1) THENIF(cin=1) THEN IF(sel=1)THEN IF(data=15) THENdata=0000;cout=1;ELSEdata=data+1;cout=0;END IF;ELSE IF(data=0000) THENdata=1111;cout=1;ELSEdata=data-1;cout=0;END IF;END IF;END IF;END IF;END PROCESS;END ARCHITECTURE example;2.循环彩灯控制器设计一个循环彩灯控制器，该控制器控制红，绿，黄三个发光管循环点亮。要求红发光管亮3秒，绿发光管亮2秒，黄发光管亮1秒。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY xhcaideng ISPORT(clk,clr:IN STD_LOGIC;red,green,yellow:OUT STD_LOGIC);END ENTITY xhcaideng;ARCHITECTURE example OF xhcaideng ISSIGNAL dout:STD_LOGIC_VECTOR(2 DOWNTO 0);SIGNAL m:STD_LOGIC_VECTOR(2 DOWNTO 0);BEGINred=dout(2);green=dout(1);yellow=dout(0);PROCESS(clk) ISBEGINIF(clr=1) THENm=001;ELSIF(clkEVENT AND clk=1) THENIF(m=110) THENm=001;ELSEmdoutdoutdoutdoutdoutdoutdout=111;END CASE;END IF;END PROCESS;END ARCHITECTURE;3.数字显示的秒表设计一块用数码管显示的秒表，能够准确的计时并显示。最大计时为59秒，最小精确到0.1秒。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity miaobiao isport(clk:in std_logic;din:in std_logic_vector(3 downto 0);wr3,wr2,wr1:in std_logic;dout3:out std_logic_vector(3 downto 0);dout2:out std_logic_vector(3 downto 0);dout1:out std_logic_vector(3 downto 0);end entity miaobiao;architecture example of miaobiao issignal out3: std_logic_vector(3 downto 0);signal out2: std_logic_vector(3 downto 0);signal out1: std_logic_vector(3 downto 0);begindout3=out3;dout2=out2;dout1=out1;process(clk) isbeginif(clkevent and clk=1) thenif(wr1=1) thenout1=din;elsif(out1=1001) thenout1=0000;elseout1=out1+1;end if;end if;end process;process(clk) isbeginif(clkevent and clk=1) thenif(wr2=1) thenout2=din;elsif(out1=1001) then if(out2=1001) thenout2=0000;else out2=out2+1;end if;end if;end if;end process;process(clk) isbeginif(clkevent and clk=1) thenif(wr3=1) thenout3=din;elsif(out1=1001) thenif(out2=1001) thenif(out3=0101) thenout3=0000;else out3=out3+1;end if;end if;end if;end if;end process;end architecture example;4.设计一个2人抢答器两人抢答，先抢为有效，用发光二极管显示是否抢到优先答题权。答题结束后，按复位键可重新抢答下一题。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity answer2 isport(reset:in std_logic;player:in std_logic_vector(2 downto 1);out1:out std_logic;out2:out std_logic;fail:out std_logic);end entity answer2;architecture example of answer2 issignal a:std_logic_vector(2 downto 0);beginout2=a(2);out1=a(1);fail=a(0);process(reset,player) isbeginif(reset=0) thenaaaaa=001;end case;end if;end process;end architecture example;5.交通灯控制器的程序设计对所提供的交通灯实验程序进行改写，原来为两个相位的交通控制转变为四个相位，即：东西直行，东西左转，南北直行，南北左转，加入一个方向显示灯的控制。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity jiaotongdeng isport(R1,G1,Y1,L1:out std_logic;R2,G2,Y2,L2:out std_logic;clk:in std_logic);end entity jiaotongdeng;architecture example of jiaotongdeng issignal m:std_logic_vector(6 downto 0):=0000000;signal n:std_logic_vector(6 downto 0):=0000000;signal a:std_logic_vector(3 downto 0);signal b:std_logic_vector(3 downto 0);beginR1=a(3);G1=a(2);Y1=a(1);L1=a(0);R2=b(3);G2=b(2);Y2=b(1);L2=b(0);AA:process(clk) isbeginif(clkevent and clk=1) thenif(m=1100100) thenm=0000001;elsem=m+1;end if;if(m=50) then a=1000;elsif(m=70) thena=0100;elsif(m=75) thena=0010;elsif(m=95) thena=0001;elsea=0010;end if;end if;end process;BB:process(clk) isbeginif(clkevent and clk=1) thenif(n=1100100) thenn=0000001;elsen=n+1;end if;if(n=20) thenb=0100;elsif(n=25) thenb=0010;elsif(n=45) thenb=0001;elsif(n=50) thenb=0010;elseb=1000;end if;end if;end process;end architecture;6. 具有使能和清零作用的16进制计数器library ieee;use ieee.std_logic_1164.all;entity count16 isport( clk :in std_logic;clear:in std_logic;enable:in std_logic;outy:out integer range 0 to 15;counter:out std_logic);end entity count16;architecture behave of count16 isbeginprocess(clk) variable cnt:integer range 0 to 15;beginif(clkevent and clk=1)thenif clear=0 thencnt:=0;elseif enable=1 thencnt:=cnt+1;end if;end if;end if;outy=cnt;if cnt=15 thencounter=1;elsecounter=0;end if;end process;end behave;7. 16路彩灯控制器library ieee;use ieee.std_logic_1164.all;package state_pack istype state is(qa,qb,qc,qd,qe,qf,qg);end state_pack;library ieee;use ieee.std_logic_1164.all;use work.state_pack.all;entity controll isport(k,s,qc1,qc2,clk:in std_logic;y,k1,k2,k3,k4,k5,k6:out std_logic);end controll;architecture rtl of controll issignal current_state:state:=qa;beginprocessbeginwait until clkevent and clk=1;if s=0 theny=0;elsey=1;end if;if k=0 thenk1=0;k2=0;k3=1;k4=1;k5=1;k6=1;current_statecurrent_state=qb;k1=1;k3if qc1=0thencurrent_state=qb;elsecurrent_state=qc;k1=0;k2if qc2=0thencurrent_state=qc;elsecurrent_state=qd;k4if qc2=0 thencurrent_state=qd;el