Verilog课程设计2

南通大学电子信息学院硬件描述语言课程设计论文课题8位ALU设计班级_集092_姓名邱小健0911002184指导教师郭兴龙日期20126182012629目录1设计概述12设计功能23设计方案34设计与仿真115硬件验证136结束语187参考文献188附录19设计概述介绍了一种基于可编程逻辑器件FPGA和硬件描述语言的8位的ALU的设计方法。该ALU采取层次设计方法，有寄存器模块，控制模块和示模块组成，能实现8位无号数的取值，加减，和4中逻辑运算，与，或，异或，同或。该ALU在QUARTUSII软件环境下进行了功能仿真，通过DE2验证表明，所设计的ALU完全正确，可供直接调用。1设计功能8位ALU设计1）本设计要求该处理器的数据宽度是8BIT，可以实现算术加法、算术减法、逻辑与、逻辑或、逻辑非、逻辑与非、逻辑或非和逻辑异或等8种运算。2）用选择端20OPCODE选择8种运算，2个操作数分别是70A_R和70B_R，运算结果是70ALU_OUT；并定义当选择端为000为取A的值、001为取B的值、010为算术加法、011为算术减法、100为逻辑与、101为逻辑或、110为逻辑异或、111为逻辑同或。3）使用DE2板上的3个拨码开关要来设置当前ALU的运算功能，再由8个拨码开关给定数据A和数据B，由一个按键KEY手动提供脉冲。2设计方案、设计说明本设计共有5个模块组成，包括1）脉冲输出器（KEY手动脉冲），计数依次产生四个脉冲到各个部件；2）寄存器A，第一个脉冲来时锁存数据A，并在数码管上显示；3）寄存器B，第二个脉冲来时锁存数据B，并在数码管上显示；4）8位ALU，；第三个脉冲来时进行运算，并所存结果ALUOUT；5）结果显示器，将结果显示在DE2板上的数码管上。RTL视图（1）顶层模块MODULEFINAL_ALU8CLK,CLK_R,RST,A,B,ALU_OUT,OPCODE,SW_AB,HEX1,HEX0,HEX7,HEX6,HEX5,HEX4INPUTCLK,RST,CLK_RINPUT70SW_ABINPUT20OPCODEOUTPUT60HEX1,HEX0,HEX7,HEX6,HEX5,HEX4OUTPUT70AOUTPUT70BOUTPUT70ALU_OUTREGAU1CLKCLK,RSTRST,SW_ABSW_AB,A_RA,CLK_RCLK_R,HEX7HEX7,HEX6HEX6REGBU2CLKCLK,RSTRST,SW_ABSW_AB,B_RB,CLK_RCLK_R,HEX5HEX5,HEX4HEX4ALURU3CLKCLK,RSTRST,A_RA,B_RB,ALU_OUTALU_OUT,OPCODEOPCODE3DIGITALU4CLK_RCLK_R,RSTRST,ALU_OUTALU_OUT,HEX1HEX1,HEX0HEX0ENDMODULE（2）寄存A值显示模块MODULEREGACLK,CLK_R,RST,SW_AB,A_R,HEX7,HEX6INPUT70SW_ABINPUTCLK,CLK_R,RSTOUTPUT70A_RREG70A_ROUTPUTREG60HEX7,HEX6REG30CNTALWAYSPOSEDGECLKORNEGEDGERSTIFRSTCNT1D0ELSEIFCNT5CNT1D0ELSECNTCNT1D1ALWAYSPOSEDGECLKORNEGEDGERSTIFRSTA_R0ELSEIFCNT1A_RSW_ABELSEA_RA_RPARAMETERSEG07B1000000,SEG17B1111001,SEG27B0100100,SEG37B0110000,SEG47B0011001,SEG57B0010010,SEG67B0000010,SEG77B1111000,SEG87B0000000,SEG97B0010000,SEGA7B0001000,SEGB7B0000011,SEGC7B1000110,SEGD7B0100001,SEGE7B0000110,SEGF7B0001110ALWAYSPOSEDGECLK_RCASEA_R304H0HEX660SEG04H1HEX660SEG14H2HEX660SEG24H3HEX660SEG344H4HEX660SEG44H5HEX660SEG54H6HEX660SEG64H7HEX660SEG74H8HEX660SEG84H9HEX660SEG94HAHEX660SEGA4HBHEX660SEGB4HCHEX660SEGC4HDHEX660SEGD4HEHEX660SEGE4HFHEX660SEGFDEFAULTHEX660SEG0ENDCASEALWAYSPOSEDGECLK_RCASEA_R744H0HEX760SEG04H1HEX760SEG14H2HEX760SEG24H3HEX760SEG34H4HEX760SEG44H5HEX760SEG54H6HEX760SEG64H7HEX760SEG74H8HEX760SEG84H9HEX760SEG94HAHEX760SEGA4HBHEX760SEGB4HCHEX760SEGC4HDHEX760SEGD4HEHEX760SEGE4HFHEX760SEGFDEFAULTHEX760SEG0ENDCASEENDMODULE（3）寄存B值显示模块MODULEREGBCLK,RST,SW_AB,B_R,CLK_R,HEX5,HEX4INPUT70SW_ABINPUTCLK,RST,CLK_ROUTPUT70B_R5REG70B_ROUTPUTREG60HEX5,HEX4REG30CNTALWAYSPOSEDGECLKORNEGEDGERSTIFRSTCNT1D0ELSEIFCNT5CNT1D0ELSECNTCNT1D1ALWAYSPOSEDGECLKORNEGEDGERSTIFRSTB_R0ELSEIFCNT2B_RSW_ABELSEB_RB_RPARAMETERSEG07B1000000,SEG17B1111001,SEG27B0100100,SEG37B0110000,SEG47B0011001,SEG57B0010010,SEG67B0000010,SEG77B1111000,SEG87B0000000,SEG97B0010000,SEGA7B0001000,SEGB7B0000011,SEGC7B1000110,SEGD7B0100001,SEGE7B0000110,SEGF7B0001110ALWAYSPOSEDGECLK_RCASEB_R304H0HEX460SEG04H1HEX460SEG14H2HEX460SEG24H3HEX460SEG34H4HEX460SEG44H5HEX460SEG54H6HEX460SEG64H7HEX460SEG74H8HEX460SEG84H9HEX460SEG94HAHEX460SEGA4HBHEX460SEGB64HCHEX460SEGC4HDHEX460SEGD4HEHEX460SEGE4HFHEX460SEGFDEFAULTHEX460SEG0ENDCASEALWAYSPOSEDGECLK_RCASEB_R744H0HEX560SEG04H1HEX560SEG14H2HEX560SEG24H3HEX560SEG34H4HEX560SEG44H5HEX560SEG54H6HEX560SEG64H7HEX560SEG74H8HEX560SEG84H9HEX560SEG94HAHEX560SEGA4HBHEX560SEGB4HCHEX560SEGC4HDHEX560SEGD4HEHEX560SEGE4HFHEX560SEGFDEFAULTHEX560SEG0ENDCASEENDMODULE（4）ALU运算模块MODULEALURCLK,RST,ALU_OUT,A_R,B_R,OPCODE,ZEROOUTPUT70ALU_OUTOUTPUTZEROINPUT70A_R,B_RINPUT20OPCODEINPUTCLK,RSTREG70ALU_OUTREG30CNTPARAMETERQUA3B000,QUB3B001,ADD3B010,DEC3B011,ANDD3B100,7XORR3B101,XOR3B110,NXOR3B111ASSIGNZEROA_RALWAYSPOSEDGECLKORNEGEDGERSTIFRSTCNT1D0ELSEIFCNT5CNT1D0ELSECNTCNT1D1ALWAYSPOSEDGECLKORNEGEDGERSTIFRSTALU_OUT0ELSEIFCNT3BEGINCASEXOPCODEQUAALU_OUTA_RQUBALU_OUTB_RADDALU_OUTA_RB_RDECALU_OUTA_RB_RANDDALU_OUTA_RXORRALU_OUTA_R|B_RXORALU_OUTA_RB_RNXORALU_OUTA_RB_RDEFAULTALU_OUT8BXXXX_XXXXENDCASEENDELSEALU_OUT0ENDMODULE（5）输出显示模块MODULEDIGITALCLK_R,RST,ALU_OUT,HEX1,HEX0INPUT70ALU_OUTINPUTCLK_R,RSTOUTPUTREG60HEX1,HEX0PARAMETERSEG07B1000000,SEG17B1111001,SEG27B0100100,SEG37B0110000,SEG47B0011001,SEG57B0010010,SEG67B0000010,8SEG77B1111000,SEG87B0000000,SEG97B0010000,SEGA7B0001000,SEGB7B0000011,SEGC7B1000110,SEGD7B0100001,SEGE7B0000110,SEGF7B0001110ALWAYSPOSEDGECLK_RCASEALU_OUT304H0HEX060SEG04H1HEX060SEG14H2HEX060SEG24H3HEX060SEG34H4HEX060SEG44H5HEX060SEG54H6HEX060SEG64H7HEX060SEG74H8HEX060SEG84H9HEX060SEG94HAHEX060SEGA4HBHEX060SEGB4HCHEX060SEGC4HDHEX060SEGD4HEHEX060SEGE4HFHEX060SEGFDEFAULTHEX060SEG0ENDCASEALWAYSPOSEDGECLK_RCASEALU_OUT744H0HEX160SEG04H1HEX160SEG14H2HEX160SEG24H3HEX160SEG34H4HEX160SEG44H5HEX160SEG54H6HEX160SEG64H7HEX160SEG74H8HEX160SEG84H9HEX160SEG994HAHEX160SEGA4HBHEX160SEGB4HCHEX160SEGC4HDHEX160SEGD4HEHEX160SEGE4HFHEX160SEGFDEFAULTHEX160SEG0ENDCASEENDMODULE10设计与仿真注仿真数字显示均采用16进制（1）取A值（控制信号【20】OPCODE000）（2）取B值（控制信号【20】OPCODE001）（3）加法运算（控制信号【20】OPCODE010）11（4）减法运算（控制信号【20】OPCODE011）（5）与逻辑运算（控制信号【20】OPCODE100）（7）或逻辑运算（控制信号【20】OPCODE101）（8）异或逻辑运算（控制信号【20】OPCODE110）（9）同或逻辑运算（控制信号【20】OPCODE111）12硬件验证（1）初始状态（2）取A值（控制信号【20】OPCODE000）13（2）取B值（控制信号【20】OPCODE001）（3）加法运算（控制信号【20】OPCODE010）14（4）减法运算（控制信号【20】OPCODE011）（6）与逻辑运算（控制信号【20】OPCODE100）15（7）或逻辑运算（控制信号【20】OPCODE101）（8）异或逻辑运算（控制信号【20】OPCODE110）16（9）同或逻辑运算（控制信号【20】OPCODE111）17结束语两个多星期的课程设计是辛苦的，是充满智慧的汗水的。我选到的课题是8位ALU设计，刚开始的时候，是一头雾水，无从下手，然后翻阅书籍和上网了解，才渐渐明白ALU是个什么，然后构建框图，设计模块，最终历时一个星期完成设计，完成之初，开心之余也发现了不足和需要改进的地方，比如A,B值不能直接显示，需要自己记忆，还有进位，输出值超过0XFF无法显