用Verilog HDL编写的四路抢答器演示幻灯片

1,四路抢答器设计,VerilogHDL语言,2,抢答器为四路，20秒倒计时，抢到后显示锁定，计时停止，若提前抢答会在另外数码管显示抢答号码。在BASYS2开发板上可以实现,3,moduleqiang_da_qi(a_to_g,A_TO_D,clk,qiang_da,button,xuan);outputwire6:0a_to_g;outputwire3:0A_TO_D;inputwireclk;/50MHz时钟wire3:0qian;wire3:0bai;wire2:0shi;wire2:0ge;wirecp;/1s时钟inputwire3:0qiang_da;inputbutton;wiresuo_1;wire2:0bian_ma_cun;wirefankui;outputwirexuan;shumaguanshumaguan0(a_to_g,A_TO_D,clk,qian,bai,shi,ge);cp_1scp_1s0(clk,cp);xuan_shouxuan_shou0(qiang_da,button,suo_1,bian_ma_cun,fankui);wei_xuanwei_xuan0(bian_ma_cun,xuan,shi,ge);fuwei_kongzhifuwei_kongzhi0(button,xuan);jishu_kongzhijishu_kongzhi0(bai,qian,cp,suo_1,xuan,fankui);endmodule,4,moduleshumaguan(a_to_g,A_TO_D,clk,qian,bai,shi,ge);/数码管驱动outputreg6:0a_to_g;outputreg3:0A_TO_D;inputwireclk;inputwire3:0qian;inputwire3:0bai;inputwire2:0shi;inputwire2:0ge;reg3:0duan;reg1:0wei;rega;reg16:0q;always(posedgeclk)beginif(q=49999)beginq=0;a=a;endelseq=q+1;end,5,always(*)/7位段译码case(duan)0:a_to_g=7b0000001;1:a_to_g=7b1001111;2:a_to_g=7b0010010;3:a_to_g=7b0000110;4:a_to_g=7b1001100;5:a_to_g=7b0100100;6:a_to_g=7b0100000;7:a_to_g=7b0001111;8:a_to_g=7b0000000;9:a_to_g=7b0000100;default:a_to_g=7b0000001;endcase,6,always(*)/4位位选译码case(wei)3:beginA_TO_D=4b1110;duan=qian;end2:beginA_TO_D=4b1101;duan=bai;end1:beginA_TO_D=4b1011;duan=shi;end0:beginA_TO_D=4b0111;duan=ge;enddefault:A_TO_D=4b1110;endcasealways(posedgea)/四个状态循环if(wei=3)wei=0;elsewei=wei+1;endmodule,7,modulecp_1s(clk,a);/提供1秒脉冲inputwireclk;outputrega;reg25:0q;always(posedgeclk)beginif(q=24999999)beginq=0;a=a;endelseq=q+1;endendmodule,8,modulexuan_shou(qiang_da,qing_ling,suo_1,bian_ma_cun,fankui);/选手抢答模块，某选手抢答后结果锁存inputwire3:0qiang_da;reg2:0bian_ma;wiresuo;inputwireqing_ling;inputwirefankui;outputreg2:0bian_ma_cun;outputwiresuo_1;always(*)begincase(qiang_da)1:bian_ma=3b001;2:bian_ma=3b010;4:bian_ma=3b011;8:bian_ma=3b100;default:bian_ma=3b000;endcaseend,9,assignsuo=(bian_ma_cun0)endendmodule,10,modulewei_xuan(bian_ma_cun,xuan,bai,ge);/控制选手是否提前抢答模块inputwire2:0bian_ma_cun;inputwirexuan;outputreg2:0bai;outputreg2:0ge;always(*)begincase(xuan)0:beginbai=bian_ma_cun;ge=3b000;end1:beginbai=3b000;ge=bian_ma_cun;enddefault:beginbai=3b000;ge=3b000;endendcaseendendmodule,11,modulefuwei_kongzhi(fu_wei,zong_kong);/复位与开始抢答的状态转换inputwirefu_wei;outputregzong_kong;always(posedgefu_wei)beginzong_kong=zong_kong;endendmodule,12,modulejishu_kongzhi(q1,q2,clk,suo,clr,fankui);/计数电路及其控制模块outputwire3:0q1;outputwire3:0q2;inputwireclk;inputwiresuo;inputwireclr;outputwirefankui;wirea;count20count20_0(a,clr,q1,q2);assignfankui=(q10endmodule,13,modulecount20(a,clr,q1,q2);/计数器，从20计到0inputwirea;inputwireclr;outputreg3:0q1;outputreg3:0q2;always(posedgeaornegedgeclr)beginif(clr=0)beginq1=4b0000;q2=4b0010;endelseif(q1=0)beginq2=q2-1;q1=9;endelseq1=q1-1;endendmodule,14,在BASYS2开发板的管脚配置：NETA_TO_D3LOC=F12;NETA_TO_D2LOC=J12;NETA_TO_D1LOC=M13;NETA_TO_D0LOC=K14;NETa_to_g6LOC=L14;NETa_to_g5LOC=H12;NETa_to_g4LOC=N14;NETa_to_g3LOC=N11;NETa_to_g2LOC=P12;NETa_to_g1LOC=L13;NETa_to_g0LOC=M12;NETqiang_da3LO