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DZD450型真空包装机设计含8张CAD图,DZD450,空包,装机,设计,CAD
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任务书 XX 学院XXXX专业论文题目 DZD450型真空包装机设计 学生姓名 XX 学 号 XX 起讫日期 20XX.2.20-2012.6.8 指导教师姓名（签名） 指导教师职称 XX 指导教师工作单位 XXXXXXXXXXXX 院（系）领导签名 下发任务书日期 ： 20XX年2月 20日题 目DZD450型真空包装机设计论文时间20XX年2月20日至 20XX年6月1日课题的主要内容及要求(含技术要求、图表要求等) 根据以下参数1. 热封条数：两条2. 真空室绝对压强： 1.332KPa 3. 最大封口有效尺寸(长宽) mm：450104. 加热温度调节范围（） ：90240 5. 加热为时间调节范围(S) :1106. 包装能力（次/小时）：1802507. 电源（三相四线制）：380V/50Hz8. 额定功率（KW）:1.39. 控制特征：人工上袋自动控制 设计一种真空包装机，完成总装图及零件。编写设计说明书；完成专业外文资料翻译1份。课题的实施的方法、步骤及工作量要求设计方法：学生在指导教师的指导下，利用所学的课程并自学有关知识，掌握机械设计的特点、方法，借助机械设计手册等技术资料，完成本机设计。设计步骤：调研收集设计资料根据所给定的参数制定总体设计方案完成总装图及部装图完成零件图编写设计说明书。 工作量要求：设计图纸工作量合计3张零号图纸（A0-2,A1-0,A2-1,A3-1,A4-13）；毕业设计说明书不少于8000汉字；外文资料原文(与课题相关的1万印刷符号左右)，外文资料翻译译文（约3000汉字）。指定参考文献 1屈能胜.我国食品包装机械发展综述M.轻工机械,2005.022金国斌.现在包装技术M.上海：上海大学出版社,20001.43钱俊，余洗，刘冬林.特种包装技术M.北京：化学工业出版社。2003.114徐灏等.机械设计手册M.北京:机械工业出版社，19915文耀平.真空包装机加热封口变压器设计计算方法J.设计探讨，19946王朝文.电热电器的设计制造与使用维修J，北京：机械工业出版社，19877习培松.张道林，四连杆真空包装机几何参数的计算J.农机与食品机械，19988王萍.真空包装机气路系统设计原理J.包装与食品机械，19989甘永利.几何公差与检测M.上海：上海工业出版社，200410成大先.机械设计手册（第七卷）M.北京:化学工业出版社,200211濮良贵,纪名刚主编.机械设计（第七版）M.北京：高等教育出版社,2001毕业设计(论文)进度计划(以周为单位) 第 1 周（2012年 2月20日-2012年 2 月 26 日）：下达设计任务书，明确任务，熟悉课题，收集资料，上交外文翻译、参考文献和开题报告。第2周第8周（2012年 2 月 27 日-2012年4 月 15 日）：制定总体方案，绘制总装图草图。第 9 周第14周（2012年4月16 日-2012年 5月 27日）：修改并完成总装图及部装图，完成有关零件图的设计。第15 周第 16 周（2012年 5 月28日-2012年 6 月5 日）：编写设计说明书第 16 周（2012年 6月 6日-2012年6 月 8 日）：准备答辩备注开题报告题目DZD450型真空包装机设计学生姓名、学号沈扬 B08152067 专业机械设计制造及其自动化（数控技术）指导教师姓名庞伟职称副教授一课题背景和意义 包装为在流通过程中保护产品，方便储运，促进销售，按一定的技术方法所用的容器、材料和辅助物等的总体名称;也指为达到_卜述目的在采用容器，材料一和辅助物的过程中施加一定技术方法等的操作活功。一件产品一般要以商品的形式经过流通后完好无损且保质保量地到达顾客手中，才能体现共功能价值和经济价值。没有包装的产品难以储存，运输和销售。包装是随着人类经济活功的发展而发展的。在当前社会，需要包装的物品种类己经越来越多，同时对包装机械的要求也越来越高。高精度，高质量，高效率的包装机往往能大幅度地增加一个企业的市场竞争力。包装机的引入甚至可以改变一个行业的生存面貌。中国白改革开放以来，包装机械行业得到了允分的发展，取得的成就也很人，然而因为起步晚，对比国外先进包装机械仍有小小差距，所以在技术领域仍然有广阔的提升空间二这就需要我们对包装机械行业给一子足够的重视和支持。基于此，我们通过刘一本课题的不断深入研究，能够在巩固和锻炼自身专业技能，熟练运用所学知识完成课题的同时，也要对包装机械行业从分类与结构组成到它未来的发展趋势有一个全局的了解。当世界各国都规定肉制品不能使用硝酸盐和亚硝酸盐作为防腐剂后，真空包装得到迅速的推广应用。使用产品范围很广，如火腿、香肠、鱼糕、咸菜、调味鱼块、鲜肉、冷冻牛排、可蒸煮袋熟肉制品、烘烤食品、果品、土特产品、药材等;后来推广到医疗器械、药品的无菌包装、化学品、精密仪器、服装、五金产品、电子元件、军工产品等各种固体、粉末装物体、液体、固液混合体包装。随着我国经济的日益发展壮大，包装工业也以年均18%的速度快速发展，但与发达国家相比，无论在产品品种、技术水平和产品质量方面都有很大差距。在我国包装工业快速发展的进程中，大量技术含量高的成套设备仍依靠进日。我国包装机械对国外高端技术的过度依赖，己成为严重制约我国包装工业持续、稳定发展的隐忧。鉴于以上原因，且包装行业又属于配套行业，涉及国民经济的许多领域，特别是食品行业与饮料行业，更是有赖于包装行业的技术进步、配套服务，因此，我们不能再忽视包装机械落后状况对我国包装行业整体发展的负面影响。真空包装机是将包装袋内抽成低真空后，当即自动封口。由于袋内的真空度高，残留的空气少，可抑制细菌等微生物的繁殖，能够延长储存期，防止食品腐败。对某些松软的食物，经过真空包装后可缩小体积。从而可使包装物品达到“四防、两省、一保质”的特点:即防潮、防霉、防污染、防氧化、省容积、省运费、延长储存期。食品包装中肉类是最适合真空包装的。采用高度防透氧的薄膜聚偏乙烯、聚酞胺、聚醋、涂以丙烯晴作为真空包装材料，可使鲜肉在包装内处于无菌状态，使其货架寿命延长1倍。各种塑料复合薄膜袋或铝箔复合薄膜袋等复合材料也适用于真空包装。真空包装机是用于包装产品，使产品增长其保质期，增加产品美观度的一种机械。真空包装技术可以提高商品的使用价值，防腐、防潮、防锈蚀，减少损耗，节约贮运费用，有利于健康。真空包装技术广泛用于食品、药品、电子仪器、精密仪表、化工产品等行业。人们膳食结构的调整和饮食习惯的改变，我国经济持续发展，促使了食品加工的快速发展，增加了高品质的包装机械和食品加工机械的需求。真空包装己经广泛的推广使用。低成本、智能化、高品质是食品包装机械的发展趋势。一台双室机可相当于两台单室机，但较两台单室机小，重量轻，可轮番作业，使准备工作与包装时间重合，因此较单室的工作效率较高，虽工作周期不变，但是排放包装件的时间与自动循环时间重合，效率可提高，成为真空包装机的又一主导产品。目前国内现有的设备存在严重的缺陷，例如:封口性能不好、真空室密封不好、包装袋的真空度不高、四连杆带动上箱室的运动不平稳、部件间连接不好、机构不可靠等缺陷，达不到理想的生产状态。鉴于这种情况，参考了一些相关的科技资料，在现有的设备的基础上，本次毕业设计对一种现有单盖双工位真空包装机进行了改进设计。单盖双工位真空包装机的关键设备是热合部件和四连杆机构，它们决定了包装袋的封口性能。因此这里所作的改进也是主要针对这两部分进行的。本课题将根据包装机的功能要求和工艺分析，参考相关的资料，分析目前真空包装设备的不足，对现有的单盖双工位真空包装机进行了改进设计。主要的改进如下:重新选用了热封变压器，提高了封口质量;对上工作室的密封槽、密封条进行了重新设计，改善了真空室的密封性;对四连杆机构进行重新设计，改善了上真空室运动的平稳性和灵活性。确定运动原理图，机械系统示意图，初定真空包装机的结构形式。重点包括真空包装机包装带供送机构设计，部件结构合理性分析和设计计算。主要零件的结构分析、材料选择、公差配合选择及技术要求说明。由于实践经验的欠缺和知识的局限性，该设备的实际工作情况及可用性还有待于实践的检验二文献综述课题依据1、 热封条数：两条2、 真空室绝对压强：1.332Kpa3、 最大封口有效尺寸（长*宽）mm：450*104、 最大封口有效范围（）：902405、 加热时间调节范围（S）：1106、 包装能力（次/小时）：1802507、 电源（三相四线制）：380V/50Hz8、 额定功率（KW）：1.39、 控制特征：人工上袋自动控制设计方法：学生在指导教师的指导下，利用所学的课程并自学有关知识，掌握机械设计的特点、方法，借助机械设计手册等技术资料，完成本机设计。设计步骤：调研收集设计资料根据所给定的参数制定总体设计方案完成总装图及部装图完成零件图编写设计说明书。工作量要求：设计图纸工作量合计3张零号图纸（A0-2张，A1-2张，A2-0张，A3-0张，A4-0张，电子手绘-若干）；毕业设计说明书不少于8000汉字；外文资料原文(与课题相关的1万印刷符号左右)，外文资料翻译译文（约3000汉字）。三参考文献1屈能胜.我国食品包装机械发展综述M.轻工机械,2005.022金国斌.现在包装技术M.上海：上海大学出版社,20001.43钱俊，余洗，刘冬林.特种包装技术M.北京：化学工业出版社.2003.114徐灏等.机械设计手册M.北京:机械工业出版社，19915文耀平.真空包装机加热封口变压器设计计算方法J.设计探讨，19946王朝文.电热电器的设计制造与使用维修J，北京：机械工业出版社，19877习培松.张道林，四连杆真空包装机几何参数的计算J.农机与食品机械，19988王萍.真空包装机气路系统设计原理J.包装与食品机械，19989甘永利.几何公差与检测M.上海：上海工业出版社，200410成大先.机械设计手册（第七卷）M.北京:化学工业出版社,2002.11濮良贵,纪名刚主编.机械设计（第七版）M.北京：高等教育出版社,2001. 学生签名： 年 月 日指导教师批阅意见（指导教师应对课题研究的思路、方法、对策、措施和预期成效等做出评价，并提出具体的改进意见） 指导教师签名： 年 月 日注：理工类学生偏重于对课题相关知识的理解和实施方案的框架结构，文管类学生偏重于对文献资料的理解与综述。表格栏高不够可自行增加。4 Stresa, Italy, 25-27 April 2007 0-LEVEL VACUUM PACKAGING RT PROCESS FOR MEMS RESONATORS Nicolas Abel1,3, Daniel Grogg1, Cyrille Hibert2, Fabrice Casset4, Pascal Ancey3, Adrian M. Ionescu1 1LEG, Ecole Polytechnique Fdrale de Lausanne (EPFL), Switzerland, 2CMI (EPFL), 3ST Microelectronics, France, 4CEA-LETI MINATEC, France ABSTRACT A new Room Temperature (RT) 0-level vacuum package is demonstrated in this work, using amorphous silicon (aSi) as sacrificial layer and SiO2 as structural layer. The process is compatible with most of MEMS resonators and Resonant Suspended-Gate MOSFET 1 fabrication processes. This paper presents a study on the influence of releasing hole dimensions on the releasing time and hole clogging. It discusses mass production compatibility in terms of packaging stress during back-end plastic injection process. The packaging is done at room temperature making it fully compatible with IC-processed wafers and avoiding any subsequent degradation of the active devices. 1. INTRODUCTION MEMS resonators performances have been demonstrated to satisfy requirements for CMOS co-integrated reference oscillator applications 2-3. Different packaging possibilities were proposed in previous years using either a 0-level approaches 4, 5 or wafer bonding approaches 6. According to industry requirements, 0-level thin film packaging using standard front-end manufacturing processes is however likely to be the most cost-efficient technique to achieve vacuum encapsulation of MEMS components for volume production. 2. DEVICE DESCRIPTION AND PACKAGING DESIGN The packaging process has been done on a MEMS resonator having MOSFET detection 1. The device is based on a suspended-gate resonating over a MOSFET channel which modulates the drain current. The advantage of this technique is the much larger the output detection current than for the usual capacitive detection type, due to the intrinsic gain of the transistor. The RSG-MOSFET device fabrication process and performances were previously described in 7. The process steps are presented in Fig. 1, where a 5m thick amorphous silicon (aSi) layer is sputtered on the already released MEMS resonator followed by a 2m RF sputtered SiO2 film deposition. A quasi-zero stress aSi film deposition process has been developed; the quasi-vertical deposition avoids depositing material under the beam lowering the releasing time. Releasing holes of 1.5m were etched through the SiO2 layer and the releasing step is done by dry SF6 plasma. Due to pure chemical etching, high selectivity of less than 1nm/min on SiO2 was obtained. The holes were clogged by a non-conformal sputters SiO2 deposition at room temperature. Fig. 1 Schematic of the 0-level vacuum package fabrication process of a RSG-MOSFET Packaging process has been performed on the metal-gate SG-MOSFET and Fig. 2a shows an SEM picture of a released AlSi-based RSG-MOSFET with a 500nm air-gap, a beam length and width of respectively 12.5m and 6m with a 40nm gate oxide. A vacuum packaged RSG-MOSFET is shown in Fig. 2b highlighting the strong bonds of the re-filled releasing hole after clogging. Cross section of a releasing hole in Fig. 2c shows more than 1m bonding surface to ensure cavity sealing. A FIB cross section in Fig. 2d shows the suspended SiO2 EDA Publishing/DTIP 2007ISBN: 978-2-35500-000-3 Nicolas Abel, Daniel Grogg, Cyrille Hibert, Fabrice Casset, Pascal Ancey, Adrian M. Ionescu 0-LEVEL VACUUM PACKAGING RT PROCESS FOR MEMS RESONATORS membrane above the suspended-gate. The vacuum atmosphere inside the cavity is obtained by depositing the top SiO2 layer under 5x10-7mBar given by the equipment. Suspended-GateDrainSourceBulk contacta)10 m DrainSourceSuspended-Gate6m1mb) SiO2c)1mHole diameter 1.5mVacuumed cavity1um SiO2d)DrainSuspended-Gate50m Fig. 2 SEM pictures of a) AlSi-based RSG-MOSFET, b) Top view of a SiO2 cap covering the RSG-MOSFET, c) Cross section of releasing holes filled with sputtered SiO2, d) FIB cross section of the packaged RSG-MOSFET, material re-deposited during the FIB cut is surrounding the suspended-gate and the SiO2 membrane. The slightly compressive SiO2 membranes show very good behavior for the thin film packaging, as seen in Fig.3 where cavities were formed on large opening size. During the clogging process, due to the highly non-conformal deposition, the amount of material entering in the cavity has been measured to be only 80nm compared to the 2.5m oxide deposited. Residues inside the cavity are confined in an 8-to-10m diameter circle, but strongly depend on the topology inside the cavity. The oxide thickness needed to clog the holes strongly depends on the hole width-over-height ratio, which therefore determines the amount of residues in the cavity. 40mSuspended SiO2membranesa) 2m1.1m aSi0.5m wet oxide4.5m sputtered SiO2b) Fig. 3 a-b)Cross section of a 2um SiO2 suspended membrane having a releasing hole clogged by a 2.5m SiO2 sputtering deposition 3. EFFECT OF OPENING SIZE ON RELEASING RATE AND CLOGGING EFFECT Etching rate variation on aSi related to the hole opening size and the aSi thickness is shown in Fig. 4. Small holes openings decrease the etching rate. A dual underetching behavior due to aSi thickness variation and holes diameters is observed after a 2 min. release step: for a small hole aperture (2m diameter), exposed surface factor is dominant and etching rate is 3 times greater for the thin aSi. However for large openings (9m diameter) for which underetch distance is more important, path factor representing the lateral opening height for species EDA Publishing/DTIP 2007ISBN: 978-2-35500-000-3 Nicolas Abel, Daniel Grogg, Cyrille Hibert, Fabrice Casset, Pascal Ancey, Adrian M. Ionescu 0-LEVEL VACUUM PACKAGING RT PROCESS FOR MEMS RESONATORS to reach aSi becomes important and then etching ratio decreases to 1.3. 012345612345678910Hole diameter (um)Underetch rate (um/min)1.1um aSi3.3 um aSi Fig. 4 Underetch rate for various releasing holes diameters with amorphous silicon sacrificial layers of 1.1m and 3.3m, after 2min. releasing. After release, encapsulation is performed by sputtered deposition of SiO2 under high vacuum of 5x10-7mbar using the intrinsic, non-conformal deposition to clog holes, as shown in Fig. 5. Clogging effect is strongly material dependent and is related to the sticking coefficient that defines probability for a molecule to stick to the surface. The coefficient is below 0.01 for LPCVD Poly-Si but 0.26 for SiO2, therefore being more suitable for clogging purpose. SiO2membrane2mCloggingHoleapertureSiO2redepositionRemaining aperture Fig. 5 Schematic of a cross section of the SiO2 membrane clogged by SiO2 sputtering deposition Hole clogging has a strong dependence on the opening aspect ratio as presented in Fig. 6. Holes with diameter-over-height aspect ratio below 1 are clogged for SiO2 thickness of 2m. Hole with opening ratio of 1.5 could only be clogged for a 3m thick SiO2 deposition. The hole clogging rate is measured to be 330nm per deposited micron of SiO2. 010002000300040000123Opening aspect ratioRemaining aperture (nm)2m SiO2Initial SiO2membrane thickness = 2m3m SiO2Remaining aperture (nm) Fig. 6 hole clogging effect depending on the diameter-over-height ratio in the 2m SiO2 membrane (Right). Remaining aperture diameter (in nm) for 2m and 3m SiO2 deposition for hole clogging. The effect of hole geometry on underetch rate and clogging has been studied on square and rectangular holes in Fig.7. Rectangular opening has a quasi identical underetching than square shape of the same opening area, while clogging is 10 times more important. 0510152025303505101520Relasing time (min)Underetch (um)2um2umx etchingdirectiony etching directionxyxx Fig. 7 Underetch length after 16min release for 29.1m2 square and rectangle release holes (red dotted rectangles). The initial SiO2 thickness is a 2m and the thickness of aSi is 1.1m. Remaining hole size after 2.5m SiO2 deposition is 1.4m for the square and 140nm for the rectangle. 4. PACKAGING ISSUES FOR PRODUCTION ENVIRONMENT For industrial production of integrated MEMS, 0-level package has to sustain plastic molding, which corresponds to an isostatic pressure of around 100Bar. Encapsulation film thickness has been designed to lower the impact of the pressure during molding. FEM simulations done with Coventor in Fig. 8 show that the EDA Publishing/DTIP 2007ISBN: 978-2-35500-000-3 Nicolas Abel, Daniel Grogg, Cyrille Hibert, Fabrice Casset, Pascal Ancey, Adrian M. Ionescu 0-LEVEL VACUUM PACKAGING RT PROCESS FOR MEMS RESONATORS molding-induced package deflection is reduced to 25nm, having a 4.5m thick SiO2 film, which makes it compatible with standard industrial back-end processes. 0 1.5 13 19 25 nmDisplacement:a)Coventor 0 0.4 0.8 1.2 1.6 MPaStress:b)Coventor Fig. 8 FEM modelling of the packaged resonator under applied isostatic pressure mimicking plastic injection process step. Effect of LTO and PECVD nitride materials on capping deflection under molding stress are presented in Table I. Membrane thickness can then be optimized to lower the molding-induced deflection by considering Youngs modulus and maximum stress before failure of the two materials. Structural layer material LTO Nitride PECVD Film thickness 4.5m 2.5m Max. stress before failure 2GPa 9GPa Stress due to molding 1.6MPa 4MPa Molding-induced deflection 25nm 36nm Table I. FEM simulations of the structural layer thickness needed to sustain plastic molding over 0-level packaging composed of a 30mx30m membrane. Comparison with PECVD nitride thickness needed to induce the same deflection. On the developed process flow, further investigations on vacuum level and long term stability still to be studied in order to fully characterize the packaging. This characterization can either be done directly by using helium leakage test 9, or indirectly by actuating the packaged resonator for which quality factor is directly related to the vacuum level. 5. CONCLUSION A novel 0-level packaging process was presented using aSi as sacrificial layer and SiO2 as encapsulating layer. RSG-MOSFET resonators have been successfully encapsulated under high vacuum. Impact of back-end-of-line indust
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