《集成电路设计实践》第四讲

1 ? ? ? Lifule Outline Introduction to full-custom design Introduction to Cadence How to create netlist for Hspice Introduction to Hspice 2 Introduction to full-custom design ? ? ? ? ? ?Full-custom? ? ?HSPICE? ? ?DRC?LVS? ? !#? !#? !#? !#? ?Cell-based? ? ? 3 Full-custom? ? composer ? Hspice ? virtuoso ? dracula ? dracula GDSII ? Hspice ? Microsim ? Netlist model Tech-file, Design rule DRC, LVS, LPE Command file ? GDSII is a format. for transferring 2D graphical-design data For LVS ? ? ?/?/? ? ? ? ?!#$%? ?A BC?DE?FGHIJK?%89?ABCD *?EF EF*GD*?HI/:;J KD=?F? Cadence layout editor: virtuoso 5 ? :N_?aP?ij$(k l)?mno ?DRC ?Design rule check ? 01 )? s?tuvwxyBz?V?m WX?4T?%TUVW?XY?Z EF*?_?+:;TU ?ab(?cd+b(e?cfgh 4ijk_?EF*lm *9Kno?*pqr stC,-:;u?VWgvw x Full-custom? ?Full-custom%? ? 2ABCD :;EF *+?,-./0 O2STMq /0 ST _ aTbCDF cdef HSPICEgh2bic d=Instance Name e?j2bSTk= Model Namee?j 2bghk +wire, wirename, pin lmpinbno HwireFM“w” Wire name 17 Wire ” +wire name wire name? H +wire? Wire name:? ? ? 18 /0?AB ?/?K pq?rst/u,MvwM“c”/ “m” ?jq# x=yxz|?=? ?Dx ?CD?C?u,=?9?O2 ?# x ?jqC?=?x? ? ?qdeleteMvwM“d”= ?O29?bx /0?AB UndoUndo?“u” ?, ? 0B?LV? K ?!? ?I!?Esc? ?_ ? ”Instance properties”?fi ?“q” 19 ?C?DE checkpin b? HIsymbol view e3Shape function ?fi ?fl b? OP/0 Symbol editor window ?check and save 21 ? pqOP lab:and2 ? =MOK? L=fail=”si.log45=C ?C?schematic :;? check and save ? ?Tk Hspice Netlist Netlist GbNetlist? =9?Hspice? ?=”?:;? 1. gnd!;?0 2. ?.subckt .ends = 1?H?.end 3. H?W?vpower vdd! 0 5 4. HI? 5. H? 6. HSTmodel 7. H?t F3f LVS 22 JKL. Hspice Netlist An example of hspice netlist .lib /spice/csmc.lib tt .options post probe .probe v(a) v(b) v(out) .trans 0.01ns 200ns uic vpower vdd! 0 5 vs1 a 0 pulse 0 5 10n 0.1n 0.1n 5n 10n vs2 b 0 pulse 0 5 20n 0.1n 0.1n 10n 20n MM5 out outn vdd! vdd! PM W=5u L=600.0n MM4 outn b vdd! vdd! PM W=5u L=600.0n MM3 outn a vdd! vdd! PM W=5u L=600.0n MM2 out outn 0 0 NM W=2u L=600.0n MM1 net17 b 0 0 NM W=4u L=600.0n MM0 outn a net17 net17 NM W=4u L=600.0n .end ? STgh ?t ? ?W I? ?schematic ? b? ? Microsim? 23 MicrosimMNO?P6QR ?=?schematic9i ?=?S? ?xN?Pspice?9i? ?license? ?CPCwindowsK?x ?PCEHspice?tx?LGEFV ?*?PC?/?AC,- ?/? Microsim ST fl setup?“? ?welcome?next ?Installation setup? ?g?#5next ?license agreement?yes 24 Microsim ST ?MicroSim Program Types? ?F?next ?schematic ? Microsim ST ?MicroSim Program ID?F ?5? pmos ?agnd ?p?bubble schematic?VW? ? ?X? HHI?(if_in,if_out) wire namelabel Analysis - Create Netlist Analysis - Examine Netlist 45?fi b? 30 XSchematics?.VW * Schematics Netlist * .EXTERNAL INPUT a .EXTERNAL INPUT b .EXTERNAL OUTPUT out M_M2 outn b vdd vdd mp L=0.6u W=5u M_M3 outn a vdd vdd mp L=0.6u W=5u M_M4 out outn vdd vdd mp L=0.6u W=5u M_U3 $N_0001 b 0 0 mn L=0.6u W=4u M_U4 out outn 0 0 mn L=0.6u W=2u M_U2 outn a $N_0001 0 mn L=0.6u W=4u $%?,?fi b node name“$ ?=$1Hspice ?2?Ll= ?e3? ? X?/0F? F3f LVS JKL. Hspice Netlist An example of hspice netlist .lib f:spiceuserlibcsmc.lib tt .options post probe .probe v(a) v(b) v(out) .trans 0.01ns 200ns uic vpower vdd 0 5 vs1 a 0 pulse 0 5 10n 0.1n 0.1n 5n 10n vs2 b 0 pulse 0 5 20n 0.1n 0.1n 10n 20n M_M2 a b vdd vdd mp L=0.6u W=5u M_M3 a N_0001 vdd vdd mp L=0.6u W=5u M_M4 out a vdd vdd mp L=0.6u W=5u M_U2 a N_0001 N_0002 0 mnL=0.6u W=4u M_U3 N_0002 b 0 0 mn L=0.6u W=4u M_U4 out a 0 0 mn L=0.6u W=2u .end ? STgh ?t ? ?W I? ?Microsim schematics? b? ? 31 Introduction to Hspice Full-custom*$?fi ? Introduction to Hspice (UNIX) VT?L|?g ?/? ?QR% ?Netlistr? ?Kspice56 ?56.7 ?V56.7? 32 ?U 1.cshrc?TGH?C? ?alias hsp2k source /net/eda450/disk2/hspice/2000.2/bin/cshrc.meta ?CD?3f?b-.? ?cdmkdir spice ?gh?csmc.lib?/spice-. ?csmc.lib?/spice?csmc.lib? .lib /spice/csmc.lib ? .lib your path/csmc.lib 1?-.?CD?-. ?cd /spice mkdir lab1 F?-.?=?*.sp ?cp /project/netlist /spice/lab1/and2.sp Netlist YZ An example of hspice netlist .lib /spice/csmc.lib tt .options post probe .probe v(a) v(b) v(out) .trans 0.01ns 200ns uic vpower vdd! 0 5 vs1 a 0 pulse 0 5 10n 0.1n 0.1n 5n 10n vs2 b 0 pulse 0 5 20n 0.1n 0.1n 10n 20n MM5 out outn vdd! vdd! PM W=5u L=600.0n MM4 outn b vdd! vdd! PM W=5u L=600.0n MM3 outn a vdd! vdd! PM W=5u L=600.0n MM2 out outn 0 0 NM W=2u L=600.0n MM1 net17 b 0 0 NM W=4u L=600.0n MM0 outn a net17 net17 NM W=4u L=600.0n .end ? STgh ?t ? ?W I? ?schematic ? b? ? 33 Netlist YZ An example of hspice netlist .lib /spice/csmc.lib tt .options post probe .probe v(a) v(b) v(out) .trans 0.01ns 200ns uic .lib /spice/csmc.lib?/? ?gh?=tt?/mosghb corner tt: typical nmos; typical pmos ff: fast nmos; fast pmos fs: fast nmos; slow pmos sf: slow nmos; fast pmos ss: slow nmos; slow pmos Graphic output for “awaves”&?* .options post ?I?7?p? .options post probe + .probe v(a) v(b) ?/?p? Netlist YZ An example of hspice netlist .lib /spice/csmc.lib tt .options post probe .probe v(a) v(b) v(out) .trans 0.01ns 200ns uic ?=? 200ns=?0.01ns ? Uic?L?)? p?=?Z? ? 6?h? .OP ?)? p? .DC vin 1V 3V 0.1V ?)? .AC DEC 1K 100MEG ?)? 34 Netlist YZ An example of hspice netlist .lib /spice/csmc.lib tt .options post probe .probe v(a) v(b) v(out) .trans 0.01ns 200ns uic vpower vdd! 0 5 vs1 a 0 pulse 0 5 10n 0.1n 0.1n 5n 10n vs2 b 0 pulse 0 5 20n 0.1n 0.1n 10n 20n Vdd! 0 5V Vpul n1 n2 pulse v1 v2 td tr tf tpw tper td tper v1 v2 tpw tftr ?W Gspice? *? ?cd /spice/lab1 ?Hsp2k ?hspice and2.sp 35 (? *?Awaves& ?cd /spice/lab1 ?awaves& (? ?q .options post probe .probe v(a) v(b) v(out) title 36 YZ? pq? ?L1overlay stacked?g?=-? ?stacked=?overlay ?F ! #b$% Waves zoomer YZ? H?F“?L&? (=F3)*+# ?btr, tf, td? 37 Introduction