数字逻辑-数字电子钟

数字跑表VerilogHDL程序顶层模块module paobiao(CLK,CLR,PAUSE,CLK,CLK1);input CLK,CLK1; / 100Hz基准时钟，1kHz数码管扫描时钟input CLR, PAUSE;output3:0 MSH,MSL,SH,SL,MH,ML;reg3:0 MSH,MSL,SH,SL,MH,ML;wire3:0 dec_in;jishi jishi(CLK,CLR,PAUSE,MSH,MSL,SH,SL,MH,ML);count10 count10(CLK,CLK1);decode4_7 decode4_7(decodeout,dec_in);segscan segscan(dec_in,MSL,MSH,SL,SL,ML,MH);endmodule时基分频器模块module count10(CLK,CLK1);input CLK1;output CLK;reg4:0 qout;always (posedge CLK1)beginif(qout9) qout=qout+1;else qout=0;endassign CLK=(qout=9)?1:0;endmodulereg CLK1;reg 4:0qunt;always (posedge CLK or negedge RST) /异步清零begin if(rst) begin qunt=5d0; end else if(qunt=5d9) begin qunt=5d0; end else begin qunt=qunt+1b1; endendwire CLK1;assign CLK1=qunt4;计时器模块/*信号定义CLK： 时钟信号；CLR： 异步复位信号；PAUSE： 暂停/启动信号；MSH，MSL：百分秒的高位和低位；SH，SL： 秒信号的高位和低位；MH，ML： 分钟信号的高位和低位。*/module jishi(CLK,CLR,PAUSE,MSH,MSL,SH,SL,MH,ML);input CLR, CLK, PAUSE;output3:0 MSH,MSL,SH,SL,MH,ML;reg3:0 MSH,MSL,SH,SL,MH,ML;reg cn1,cn2; /cn1为百分秒向秒的进位，cn2为秒向分的进位/*百分秒计数进程，每计满100，cn1产生一个进位1*always(posedge CLK or posedge CLR)begin if(CLR) begin /异步复位MSH,MSL=8h00; cn1=0; end else if(!PAUSE) /PAUSE为0时正常计数，为1时暂时计数 begin if(MSL=9) /百分秒低位是否为9 begin MSL=0; if(MSH=9) begin MSH=0; cn1=1; end else MSH=MSH+1; cn1=0; end else begin MSL=MSL+1; cn1=0; end endend/*秒计数进程，每计满60，cn2产生一个进位*always(posedge cn1 or posedge CLR)begin if(CLR) /异步复位 begin SH,SL=8h00; cn2=0; end else if(SL=9) /低位是否为9 begin SL=0; if(SH=5) begin SH=0; cn2=1; end else SH=SH+1; cn2=0; end else begin SL=SL+1; cn2=0; endend/*分钟计数进程，每计满60，系统自动清零*always(posedge cn2 or posedge CLR)begin if(CLR) /异步复位begin MH,ML=8h00; endelse if(ML=9) begin ML=0; if(MH=5) begin MH=0; end else MH=MH+1; end else ML3d7) ss=0; else ss=ss+1; end always(posedge CLK1)begin case(ss) 3d5: dec_in=MSL; 3d4:dec_in=MSH; 3d3:dec_in=SL; 3d2:dec_in=SH; 3d1:dec_in=ML; 3d0:dec_in=MH; 3d6:dec_in=3d0; 3d7:dec_in=3d0; endcase end endmoduleBCD/七段译码模块moudle decode4_7(decodeout,dec_in)input3:0 dec_in;output6:0 decodeout;reg6:0 decodeout;always( dec_in) /用case语句进行译码 begin case(dec_in) /decodeout610分别对应数码管的ag 4d0:decodeout=7b;/显示0 4d1:decodeout=7b;/显示1 4d2:decodeout=7b; 4d3:decodeout=7b; 4d4:decodeout=7b; 4d5:decodeout=7b; 4d6: