VHDL双语教学第3章.ppt

VHDL,Synthesisuseieee.std_logic_1164.all;-entityXYZisport(A,B,C:instd_logic;-CommentsF:outstd_logic);endXYZ;-architectureXYZ_archofXYZisbeginF=(AandB)or(BandC)or(CandA);endXYZ_arch;,Agenda,OverviewEntityKeywordsPortGenericArchitectureLibraryuseieee.std_logic_1164.all;-entityXYZisport(A,B,C:instd_logic;F:outstd_logic);endXYZ;-architectureXYZ_archofXYZisbeginF=(AandB)or(BandC)or(CandA);endXYZ_arch;,EntityDefinition,entityentity_nameisGenerics;Ports;OtherDeclarativeParts;Statements;endentityentity_name;,EntityExamples(ROM),entityROMisport(D0:outbit;D1:outbit;D2:outbit;D3:outbit;D4,D5,D6,D7:outbit;A:inbit_vector(7downto0);endROM;,A0A1A2A3A4A5A6A7,D0D1D2D3D4D5D6D7,EntityExamples(Adder),entityFull_Adderisport(X,Y,Cin:inBit;Cout,Sum:outBit);endentityFull_Adder;,XYCin,SumCout,EntityExamples(n-inputAND),entityANDNisgeneric(wid:integer:=2);port(X:inbit_vector(wid-1downto0);F:outbit);end;,EntityExample(EmptyEntity),entityTest_BenchisendentityTest_Bench;,Test_Bench,SignalGenerator,TestTarget,Agenda,OverviewEntityKeywordsPortGenericArchitectureLibraryPorts;OtherDeclarativeParts;Statements;endentityentity_name;,PortExample(ANDN),entityANDNisgeneric(wid:integer:=2);port(X:inbit_vector(wid-1downto0);F:outbit);end;,PortExamples(ROM),entityROMisport(D0:outbit;D1:outbit;D2:outbit;D3:outbit;D4,D5,D6,D7:outbit;A:inbit_vector(7downto0);endROM;,PortExamples(Adder),entityFull_Adderisport(X,Y,Cin:inBit;Cout,Sum:outBit);endentityFull_Adder;,XYCin,SumCout,PortExamples(n-inputAND),entityANDNisgeneric(wid:integer:=2);port(X:inbit_vector(wid-1downto0);F:outbit);end;,PortDefinition,Port(Port_Name,Port_Name:DirType:=Default_Val;Port_Name,Port_Name:DirType:=Default_Val;.Port_Name,Port_Name:DirType:=Default_Val;);,EachPartsofPort,port(A0,A1:instd_logic;A2:instd_logic:=1;F0:bufferstd_logic;F1:outstd_logic;F2:inoutstd_logic);,PortNameDirTypeDefaultValue,Typeof“Dir”,InOutInoutBufferLinkage,SignalDirection,OtherIC,OtherIC,DirExample,port(A0,A1:instd_logic;A2:instd_logic:=1;F0:bufferstd_logic;F1:outstd_logic;F2:inoutstd_logic);,UseofDir,libraryieee;useieee.std_logic_1164.all;-entityABCisport(A0,A1,A2:instd_logic;F0:bufferstd_logic;F1:outstd_logic;F2:inoutstd_logic);endABC;,-architectureABC_archofABCisbeginprocess(A0)beginifrising_edge(A0)thenF0=notF0;F1=F2;endif;endprocess;F2=A1whenA2=1ELSEZ;endABC_arch;,Type,port(A0,A1:instd_logic;A2:instd_logic:=1;F0:bufferstd_logic;F1:outstd_logic;F2:inoutstd_logic);,PortNameDirTypeDefaultValue,TypicalPortType,BitBit_vectorStd_logicStd_logic_vector,Bit,10,Bit_vector,port(X:inbit_vector(3downto0);F:outbit);,Port(X0:inbit;X1:inbit;X2:inbit;X3:inbit;F:outbit);,Port(X0,X1,X2,X3:inbit;F:outbit);,Std_logic,U,-UninitializedX,-ForcingUnknown0,-Forcing01,-Forcing1Z,-HighImpedanceW,-WeakUnknownL,-Weak0H,-Weak1-Dontcare,ResolutionFunctionOfStd_logic,Std_logic_vector,port(X:instd_logic_vector(3downto0);F:outstd_logic);,Agenda,OverviewEntityKeywordsPortGenericArchitectureLibraryPorts;OtherDeclarativeParts;Statements;endentityentity_name;,AnANDGateWithUnknownInputs,entityANDNisgeneric(wid:integer:=2);port(X:inbit_vector(wid-1downto0);F:outbit);endANDN;,GenericDefinition,generic(Name,Name:DataType:=DefaultValue;Name,Name:DataType:=DefaultValue;.Name,Name:DataType:=DefaultValue);,GenericExample(1),entityabcdisgeneric(p_a:integer:=2;p_b:integer:=7);port(A:outbit_vector(0top_a-1);F:inbit);end;,UseoftheGeneric(ANDN.vhd),libraryieee;useieee.std_logic_1164.all;-entityANDNisgeneric(wid:integer:=2);port(X:inbit_vector(wid-1downto0);F:outbit);endANDN;-architectureANDN_archofANDNisbeginprocess(X)variabletmp:bit;begintmp:=1;foriinwid-1downto0looptmp:=tmpandX(i);endloop;F=tmp;endprocess;endANDN_arch;,UseoftheGeneric(My_package.vhd),libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;-packagemy_packageiscomponentANDNisgeneric(wid:integer:=2);port(X:inbit_vector(wid-1downto0);F:outbit);endcomponent;endmy_package;,libraryieee;useieee.std_logic_1164.all;librarywork;usework.my_package.all;-entitySEEisport(A:inbit_vector(3downto0);B:inbit_vector(1downto0);F1,F2:outbit);endSEE;-architectureSEE_archofSEEisbeginU1:ANDNgenericmap(4)portmap(A,F1);U2:ANDNportmap(B,F2);endSEE_arch;,UseoftheGeneric(see.vhd),Agenda,OverviewEntityArchitectureKeywordsBlockProcessSubprogramFunctionProcedureLibraryuseieee.std_logic_1164.all;-entityXYZisport(A,B,C:instd_logic;F:outstd_logic);endXYZ;-architectureXYZ_archofXYZisbeginF=(AandB)or(BandC)or(CandA);endXYZ_arch;,ArchitectureDefinition,architecturearch_nameofentity_nameisarchitecture_declarative_partbeginarchitecture_statement_partendarchitecturearch_name;,ArchitectureExample(ABC.vhd),libraryieee;useieee.std_logic_1164.all;-entityABCisport(A0,A1,A2:instd_logic;F0:bufferstd_logic;F1:outstd_logic;F2:inoutstd_logic);endABC;,-architectureABC_archofABCisbeginprocess(A0)beginifrising_edge(A0)thenF0=notF0;F1=F2;endif;endprocess;F2=A1whenA2=1ELSEZ;endABC_arch;,ArchitectureExample(ANDN.vhd),libraryieee;useieee.std_logic_1164.all;-entityANDNisgeneric(wid:integer:=2);port(X:inbit_vector(wid-1downto0);F:outbit);endANDN;-architectureANDN_archofANDNisbeginprocess(X)variabletmp:bit;begintmp:=1;foriinwid-1downto0looptmp:=tmpandX(i);endloop;F=tmp;endprocess;endANDN_arch;,UseoftheGeneric(see.vhd),libraryieee;useieee.std_logic_1164.all;librarywork;usework.my_package.all;-entitySEEisport(A:inbit_vector(3downto0);B:inbit_vector(1downto0);F1,F2:outbit);endSEE;-architectureSEE_archofSEEisbeginU1:ANDNgenericmap(4)portmap(A,F1);U2:ANDNportmap(B,F2);endSEE_arch;,Agenda,OverviewEntityArchitectureKeywordsBlockProcessSubprogramFunctionProcedureLibraryuseieee.std_logic_1164.all;-entityblkblkisport(X:instd_logic;Y:outstd_logic);endblkblk;,architectureblkblk_archofblkblkissignalA,B:std_logic;beginu1:blocksignalC,D:std_logic;beginA=C;B=D;C=X;D=X;endblocku1;u2:blocksignalC,E:std_logic;beginC=A;E=B;u3:blocksignalE,F,G:std_logic;beginE=A;F=E;G=u2.E;endblocku3;endblocku2;Y=Xand(AorB);endblkblk_arch;,DefinitionofBlock,BlockLabel:block(GuardExpression)isDeclarations;beginConcurrentStatements;endblockBlockLabel;,ExampleofBlock(BLKBLK.vhd),libraryieee;useieee.std_logic_1164.all;-entityblkblkisport(X:instd_logic;Y:outstd_logic);endblkblk;,architectureblkblk_archofblkblkissignalA,B:std_logic;beginu1:blocksignalC,D:std_logic;beginA=C;B=D;C=X;D=X;endblocku1;u2:blocksignalC,E:std_logic;beginC=A;E=B;u3:blocksignalE,F,G:std_logic;beginE=A;F=E;G=u2.E;endblocku3;endblocku2;Y=Xand(AorB);endblkblk_arch;,ExampleofBlock(Test_16.vhd),beginBlck_Test_1:block(clock=1andClockEVENT)beginDestination_1=guardedSource;Destination_2=Source;endblockBlck_Test_1;Blck_Test_2:block(Clock=1andnot(ClockSTABLE)beginDestination_3=guardedSource;Destination_4=Source;endblockBlck_Test_2;Monitor:processvariableSource_Var:NATURAL;variableDest_1_Var,Dest_2_Var:NATURAL;variableDest_3_Var,Dest_4_VAr:NATURALbeginSource_Var:=Source;Dest_1_Var:=Destination_1;Dest_2_Var:=Destination_2;Dest_3_Var:=Destination_3;Dest_4_Var:=Destination_4;waitonDestination_1,Destination_2,Destination_3,Destination_4;endprocessMonitor;Tick_Tock:processbeginwaitfor10ns;Clock=notclock;endprocessTick_Tock;Source_Wave:Source=1after8ns,2after15ns,3after16ns,4after17ns,5after18ns,6after19ns;endBehave_1;,entityTest_16isendTest_16;architectureBehave_1ofTest_16issignalSource:NATURAL:=0;signalDestination_1:NATURAL:=0;signalDestination_2:NATURAL:=0;signalDestination_3:NATURAL:=0;signalDestination_4:NATURAL:=0;signalClock:BIT:=0;,GuardedSignalsInBlock,BlockLabel:block(GuardExpression)isDeclarations;beginConcurrentStatements;endblockBlockLabel;,GuardedSignalsExample(LT1.vhd),libraryieee;useieee.std_logic_1164.all;entityLT1isport(D,CLK:inbit;Q:outbit;Free_in:inbit;Free_out:outbit);endLT1;architectureLT1_archofLT1isbeginU1:blockbeginQ=guardedD;Free_out=notFree_in;endblockU1;endLT1_arch;,Q=D;,Free_out=notFree_in;,DCLKFree_in,QFree_out,GuardedSignalsExample(LT.vhd),libraryieee;useieee.std_logic_1164.all;entityLTisport(D,CLK:inbit;Q:outbit;Free_in:inbit;Free_out:outbit);endLT;architectureLT_archofLTisbeginU1:block(CLK=1)beginQ=guardedD;Free_out=notFree_in;endblockU1;endLT_arch;,Q=guardedD;,Free_out=notFree_in;,GuardedSignalsExample(Wave),Agenda,OverviewEntityArchitectureKeywordsBlockProcessSubprogramFunctionProcedureLibrary,ExampleofProcess(Test_16.vhd),beginBlck_Test_1:block(clock=1andClockEVENT)beginDestination_1=guardedSource;Destination_2=Source;endblockBlck_Test_1;Blck_Test_2:block(Clock=1andnot(ClockSTABLE)beginDestination_3=guardedSource;Destination_4=Source;endblockBlck_Test_2;Monitor:processvariableSource_Var:NATURAL;variableDest_1_Var,Dest_2_Var:NATURAL;variableDest_3_Var,Dest_4_VAr:NATURALbeginSource_Var:=Source;Dest_1_Var:=Destination_1;Dest_2_Var:=Destination_2;Dest_3_Var:=Destination_3;Dest_4_Var:=Destination_4;waitonDestination_1,Destination_2,Destination_3,Destination_4;endprocessMonitor;Tick_Tock:processbeginwaitfor10ns;Clock=notclock;endprocessTick_Tock;Source_Wave:Source=1after8ns,2after15ns,3after16ns,4after17ns,5after18ns,6after19ns;endBehave_1;,entityTest_16isendTest_16;architectureBehave_1ofTest_16issignalSource:NATURAL:=0;signalDestination_1:NATURAL:=0;signalDestination_2:NATURAL:=0;signalDestination_3:NATURAL:=0;signalDestination_4:NATURAL:=0;signalClock:BIT:=0;,ExampleofProcess(Test_16.vhdzoom),Monitor:processvariableSource_Var:NATURAL;variableDest_1_Var,Dest_2_Var:NATURAL;variableDest_3_Var,Dest_4_VAr:NATURALbeginSource_Var:=Source;Dest_1_Var:=Destination_1;Dest_2_Var:=Destination_2;Dest_3_Var:=Destination_3;Dest_4_Var:=Destination_4;waitonDestination_1,Destination_2,Destination_3,Destination_4;endprocessMonitor;Tick_Tock:processbeginwaitfor10ns;Clock=notclock;endprocessTick_Tock;,ProcessExampleWithSensitiveTable(MY_DFF.vhd),libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;-entityMY_DFFisport(D,CP:instd_logic;Q:outstd_logic);endMY_DFF;,architectureMY_DFF_archofMY_DFFisbeginprocess(CP)beginifrising_edge(CP)thenQ=D;endif;endprocess;endMY_DFF_arch;,ProcessExampleWithWait(MY_DFF.vhd),architectureMY_DFF_archofMY_DFFisbeginprocessbeginwaituntilCPeventandCP=1;Q=D;endprocess;endMY_DFF_arch;,ProcessExample(Latch.vhd),libraryieee;useieee.std_logic_1164.all;-entityLTisport(D,CLK:inbit;Q:outbit);endLT;,architectureLT_archofLTisbeginprocess(CLK,D)beginifCLK=1thenQ=D;endif;endprocess;endLT_arch;,Process(PROC2Diagram),ProcessExample(Proc2.vhd),libraryieee;useieee.std_logic_1164.all;-entityPROC2isport(X:instd_logic);endPROC2;,architecturePROC2_archofPROC2issignalto_a,to_b:std_logic:=0;beginPA:process(X,to_a)beginif(XeventandX=1)or(to_aeventandto_a=1)thento_b=1after20ns,0after30ns;endif;endprocessPA;PB:process(to_b)beginif(to_beventandto_b=1)thento_a=1after10ns,0after20ns;endif;endprocessPB;endPROC2_arch;,PA:process(X,to_a)beginif(XeventandX=1)or(to_aeventandto_a=1)thento_b=1after20ns,0after30ns;endif;endprocessPA;,PB:process(to_b)beginif(to_beventandto_b=1)thento_a=1after10ns,0after20ns;endif;endprocessPB;,ProcessExample(Proc2Wave),Agenda,OverviewEntityArchitectureKeywordsBlockProcessSubprogramFunctionProcedureLibrary,functionName(ParamList)returnTypeisDeclarativePart;beginStatementPart;endfunctionName;,Declaration,Body,FunctionsExample(My_Package.vhd),libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;-packagemy_packageisendmy_package;,functionSUM2(S1,S2:instd_logic_vector)returnstd_logic_vector;,packagebodymy_packageisendmy_package;,functionSUM2(S1,S2:instd_logic_vector)returnstd_logic_vectorisvariabletmp:std_logic_vector(S1range);begintmp:=S1+S2;returntmp;endSUM2;,FunctionCallExample,libraryieee;useieee.std_logic_1164.all;librarywork;usework.my_package.all;-entitySUBPROCisport(X:instd_logic_vector(3downto0);Y:instd_logic_vector(3downto0);Z:outstd_logic_vector(3downto0);endSUBPROC;architectureSUBPROC_archofSUBPROCisbeginZ=SUM2(X,Y);endSUBPROC_arch;,Agenda,OverviewEntityArchitectureKeywordsBlockProcessSubprogramFunctionProcedureLibrarybeginStatementPart;endprocedureName;,Declaration,Body,ProcedureExample(My_Pachage.vhd),libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;-packagemy_packageisendmy_package;,packagebodymy_packageisendmy_package;,procedureNOT_PROC(A:instd_logicC:outstd_logic);,procedureNOT_PROC(A:instd_logic;B:outstd_logic)isbeginB:=notA;endNOT_PROC;,ProcedureCallExample,libraryieee;useieee.std_logic_1164.all;librarywork;usework.my_package.all;-entitySUBPROCisport(M:instd_logic;CLK:instd_logic;K:outstd_logic);endSUBPROC;,architectureSUBPROC_archofSUBPROCisbeginProcess(CLK)variabletmp:std_logic;beginifrising_edge(CLK)thenNOT_PROC(M,tmp);K=tmp;endif;endprocess;endSUBPROC_arch;,Agenda,OverviewEntityArchitectureLibraryuseLibraryName.PackageName.ItemName;useLibraryName.PackageName.all;useLibraryName.ItemName;useLibraryName.all;,Libraryuseieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;librarywork;usework.my_package.all;,Agenda,OverviewEntityArchitectureFunctionProcedureLibraryendpackagePackageName;,packagebodyPackageNameisPackageBody;endpackagebodyPackageName;,Declaration,Body,Apackagefilehas2Parts,DeclarationpartsandBodyparts,PackageExample(sub-program),libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;-packagemy_packageisfunctionSUM2(S1,S2:instd_logic_vector)returnstd_logic_vector;procedureNOT_PROC(A:instd_logic;B:outstd_logic);endmy_package;,packagebodymy_packageisfunctionSUM2(S1,S2:instd_logic_vector)returnstd_logic_vectorisvariabletmp:std_logic_vector(S1range);begintmp:=S1+S2;returntmp;endSUM2;procedureNOT_PROC(A:instd_logic;B:outstd_logic)isbeginB:=notA;endNOT_PROC;endmy_package;,PackageDeclarations,packagePackageNameisProcedureDeclaration;FunctionDeclearation;ComponentDeclaration;SubtypeDeclaration;ConstantDeclaration;SignalDeclaration;FileDeclaration;AliasDeclaration;AttributeDeclaration;endpackagePackageName;,Declaration,PackageExample(sub-program),libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;-packagemy_packageisfunctionSUM2(S1,S2:instd_logic_vector)returnstd_logic_vector;procedureNOT_PROC(A:instd_logic;B:outstd_logic);endmy_package;,packagebodymy_packageisfunctionSUM2(S1,S2:instd_logic_vector)returnstd_logic_vectorisvariabletmp:std_logic_vector(S1range);begintmp:=S1+S2;returntmp;endSUM2;procedureNOT_PROC(A:instd_logic;B:outstd_logic)isbeginB:=notA;endNOT_PROC;endmy_package;,PackageExample(Component),libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;-packagemy_packageiscomponentANDNisgeneric(wid:integer:=2);port(X:inbit_vector(wid-1downto0);F:outbit);endcomponent;endmy_package;,entityANDNisgeneric(wid:integer:=2);port(X:inbit_vector(wid-1downto0);F:outbit);end;,PackageExample(Typeuseieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;-packagemy_packageisconstantconst_K:integer:=100;typestate_typeis(idle,s0,s1,s2,s3);subtypeByteisStd_logic_vector(7downto0);componentXYZisport(A,B,C:instd_logic;F:outstd_logic);endcomponent;componentANDNisgeneric(wid:integer:=2);port(X:inbit_vector(wid-1downto0);F:outbit);endcomponent;functionSUM2(S1,S2:instd_logic_vector)returnstd_logic_vector;procedureNOT_PROC(A:instd_logic;B:outstd_logic);endmy_package;,packagebodymy_packageisfunctionSUM2(S1,S2:instd_logic_vector)returnstd_logic_vectorisvariabletmp:std_logic_vector(S1range);begintmp:=S1+S2;returntmp;endSUM2;procedureNOT_PROC(A:instd_logic;B:outstd_logic)isbeginB:=notA;endNOT_PROC;endmy_package;,TypesendconfigurationConfigName;,ConfigurationExample(WHAT.vhd),libraryieee;useieee.std_logic_1164.all;-entityWHATisport(A,B:inbit;F:outbit);endWHAT;entityWHOisport(X:inbit;Y:outbit);endWHO;-,architectureWHAT_arch0ofWHATisbeginF=AandB;endWHAT_arch0;architectureWHAT_arch1ofWHATisbeginF=AorB;endWHAT_arch1;architectureWHAT_arch2ofWHATisbeginF=AxorB;endWHAT_arch2;architectureWHO_arch0ofWHOisbeginY=notX;endWHO_arch0;architectureWHO_arch1ofWHOisbeginY=X;endWHO_arch1;,configurationWHO_conf0ofWHOisforWHO_arch0endfor;endWHO_co