传动箱侧盖机械加工及其数控加工编程[三维PROE]【含CAD图纸+PDF图】
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三维PROE
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AT89C2051 DescriptionThe AT89C2051 is a low-voltage, high-performance CMOS 8-bit micr-ocomputer with 2 Kbytes of Flash programmable and erasable read only m-emory (PEROM). The device is manufactured using Atmels high density nonvolatile memory technology and is compatible with the industry standar-d MCS-51 instruction set and pinout. By combining a versatile 8-bit CP-U with Flash on a monolithic chip, the Atmel AT89C2051 is a powerful microcomputer which provides a highly flexible and cost effective solutiont-o many embedded control applications.The AT89C2051 provides the following standard features: 2 Kbytes ofFlash, 128 bytes of RAM, 15 I/O lines, two 16-bit timer/counters, a five v-ector two-level interrupt architecture, a full duplex serial port, a precision analog comparator, on-chip oscillator and clock circuitry. In addition, the A-T89C2051 is designed with static logic for operation down to zero freque-ncy and supports two software selectable power saving modes. The Idle M-ode stops the CPU while allowing the RAM, timer/counters, serial port an-d interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functio-ns until the next hardware reset. Pin Configuration：Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverti-ng amplifier which can be configured for use as an on-chip oscillator, as s-hown in Figure 1. Either a quartz crystal or ceramic resonator may beused. To drive the device from an external clock source, XTAL2 should b-eleft unconnected while XTAL1 is driven as shown in Figure 2. There ar-eno requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop,but minimum and maximum voltage high and low time specifications mustbe observed.Restrictions on Certain InstructionsThe AT89C2051 and is an economical and cost-effective member of Atmels growing family of microcontrollers. It contains 2 Kbytes of flash program memory. It is fully compatible with the MCS-51 architecture, andcan be programmed using the MCS-51 instruction set. However, there are a few considerations one must keep in mind when utilizing certain instructions to program this device.All the instructions related to jumping or branching should be restricte-d such that the destination address falls within the physical program mem-ory space of the device, which is 2K for the AT89C2051. This should be the responsibility of the software programmer. For example, LJMP 7E0H would be a valid instruction for the AT89C2051 (with 2K of memory), w-hereas LJMP 900H would not.1. Branching instructions:LCALL, LJMP, ACALL, AJMP, SJMP, JMP A+DPTR These uncon-ditional branching instructions will execute correctly as long as the progra-mmer keeps in mind that the destination branching address must fall withi-n the physical boundaries of the program memory size (locations 00H to 7FFH for the 89C2051). Violating the physical space limits may cause unkn-own program behavior.CJNE ., DJNZ ., JB, JNB, JC, JNC, JBC, JZ, JNZ With these c-onditional branching instructions the same rule above applies. Again, violat-ing the memory boundaries may cause erratic execution.For applications involving interrupts the normal interrupt service routin-e address locations of the 80C51 family architecture have been preserved.2. MOVX-related instructions, Data Memory:The AT89C2051 contains 128 bytes of internal data memory. Thus, inthe AT89C2051 the stack depth is limited to 128 bytes, the amount of ava-ilable RAM. External DATA memory access is not supported in this devi-ce, nor is external PROGRAM memory execution. Therefore, no MOVX . instructions should be included in the program. A typical 80C51 assembler will still assemble instructions, even if the-y are written in violation of the restrictions mentioned above. It is the res-ponsibility of the controller user to know the physical features and limitati-ons of the device being used and adjust the instructions used correspondin-gly.Program Memory Lock BitsOn the chip are two lock bits which can be left unprogrammed (U) o-r can be programmed (P) to obtain the additional features listed in the ta-ble below:Lock Bit Protection ModesProgram Lock BitsLB1 LB2Protection Type1 U UNo program lock features2 P UFurther programming of the Flash is disabled.3 P PSame as mode 2, also verify is disabled.Note:1.The Lock Bits can only be erased with the Chip Erase operationIdle ModeIn idle mode, the CPU puts itself to sleep while all the onchip periph-erals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or b-y a hardware reset.P1.0 and P1.1 should be set to 0 if no external pullups are used, or set to 1 if external pullups are used.It should be noted that when idle is terminated by a hardware reset, t-he device normally resumes program execution, from where it left off, up-to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access tothe port pins is not inhibited. To eliminate the possibility of an unexpectedwrite to a port pin when Idle is terminated by reset, the instruction follow-ing the one that invokes Idle should not be one that writes to a port pin-or to external memory.Power Down ModeIn the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RA-M and Special Function Registers retain their values until the power downmode is terminated. The only exit from power down is a hardware reset.R-eset redefines the SFRs but does not change the onchip RAM. The reset should not be activated before VCC is restored to its normal operatin-g level and must be held active long enough to allow the oscillator to res-tart and stabilize.P1.0 and P1.1 should be set to 0 if no external pullups are used, or set to 1 if external pullups are used.Programming The FlashThe AT89C2051 is shipped with the 2 Kbytes of on-chip PEROM co-de memory array in the erased state (i.e., contents = FFH) and ready to b-e programmed. The code memory array is programmed one byte at a tim-e. Once the array is programmed, to re-program any non-blank byte, the e-ntire memory array needs to be erased electrically.Internal Address Counter: The AT89C2051 contains an internal PEROM address counter which is always reset to 000H on the rising edge of RST and is advanced by applying a positive going pulse to pin XTAL1.Data Polling: The AT89C2051 features Data Polling to indicate the end ofa write cycle. During a write cycle, an attempted read of the last byte wri-tten will result in the complement of the written data on P1.7. Once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycl-e has been initiated.Ready/Busy: The Progress of byte programming can also be monitored by the RDY/BSY output signal. Pin P3.1 is pulled low after P3.2 goes Highduring programming to indicate BUSY. P3.1 is pulled High again when pr-ogramming is done to indicate READY.Program Verify: If lock bits LB1 and LB2 have not been programmed co-de data can be read back via the data lines for verification:1. Reset the internal address counter to 000H by bringing RST fromLto H.2. Apply the appropriate control signals for Read Code data and read the output data at the port P1 pins.3. Pulse pin XTAL1 once to advance the internal address counter.4. Read the next code data byte at the port P1 pins.5. Repeat steps 3 and 4 until the entire array is read. The lock bits canno-t be verified directly. Verification of the lock bits is achieved by observin-g that their features are enabled.Chip Erase: The entire PEROM array (2 Kbytes) and the two Lock Bits are erased electrically by using the proper combination of control signals a-nd by holding P3.2 low for 10 ms. The code array is written with all “1-s in the Chip Erase operation and must be executed before any nonblankmemory byte can be re-programmed.Reading the Signature Bytes: The signature bytes are read by the same p-rocedure as a normal verification of locations 000H, 001H, and 002H, exc-ept that P3.5 and P3.7 must be pulled to a logic low. The values returne-dare as follows.(000H) = 1EH indicates manufactured by Atmel(001H) = 21H indicates 89C2051Programming Interface：Every code byte in the Flash array can be written and the entire arra-y can be erased by using the appropriate combination of control signals. T-he write operation cycle is self-timed and once initiated, will automaticallytime itself to completion. AT89C2051功能特性：AT89C2051是一种低电压，高性能CMOS 8位单片机，片内含2k bytes的可反复擦写的只读程序存储器（PEROM）和128 bytes的随机随取数据存储器（RAM），器件采用ATMEL 公司的高密度，非易失性存储技术生产，兼容标准MCS-51指令系统，片内置通用8位中央处理器和Flash 存储单元，功能强大AT89C2051单片机可为您提供许多高性价比的应用场合。AT89C2051提供以下标准功能：2k字节Flash闪速存储器，128字节内部RAM，15个I/O口线，两个16位定时/计数器，一个5向量两级中断结构，一个全双工串行通信口，内置一个精密比较器，片内振荡器及时钟电路。同时，AT89C2051可降至0Hz的表态逻辑操作，并支持两种软件可选的节电工作模式。空闲方式停止CPU的工作，但允许RAM，定时/计数器，串行通信及中断系统继续工作。掉电方式保存RAM中的内容，但振荡器停止工作并禁止其它所有部件工作直到下个硬件复位。引脚结构如下振荡器特征：XTAL1、 XTAL2为片内振荡器的反相放大器的输入和输出端，如下图所示。可采用石英晶体或陶瓷振荡器组成时钟振荡器，如需从外部输入时钟驱动AT89C2051，时钟信号从XTAL1输入，XTAL2应悬空。由于输入到内部电路经过一个2分频触发器，所以输入的外部时钟信号无需要特殊要求，但它必须符合电平的最大和最小值及时序规范。某些指令的约束条件：AT89C2051是经济型低价位的微控制器，它含有2k字节的Flash闪速程序存储器，指令系统与MCS51完全兼容，可使用MCS51指令系统对其进行编程。但是在使用某些有关指令编程时，程序员须注意一些事项。和跳转或分支有关的指令有一定的空间约束，使目的地址能安全落在AT89C2051的2k字节的物理程序存储器空间内，程序员必须注意这一点。对于2k字节存储器的AT89C2051来说，LJMP 7E0H是一条有效指令，而LJMP 900H则为无效指令。1分支指令： 对于LCALL、LJMP、ACALL、AJMP、SJMP、JMP+DPTR等指令，只要程序员记住这些分支指令的目的地址在程序存储器大小的物理范围内（AT89C2051程序地址空间为：000H7FFH单元），这些无条件分支就会正确执行，超出物理空间的限制会出现不可预知的程序出错。CJNE、DJNZ、JB、JNB、JC、JNC、JBC、JZ、JNZ等这些条件转移指令的使用与上述原则一样，同样，超出物理空间的限制也会引起不可预知的程序出错。至于中断的使用，80C51系列硬件结构中已保留标准中断服务子程序的地址。2与MOVX相关的指令，数据存储器：AT89C2051包含128字节内部数据存储器，这样，AT89C2051的堆栈深度局限于内部RAM的128字节范围内，它既不支持外部数据存储器的访问，也不支持外部程序存储器的执行，因此程序中不应有MOVX指令。一般的80C51汇编器即使在违反上述指令约束而写入指令时仍对指令进行汇编，用户应了解正在使用的AT89C2051微控制器的存储器物理空间和约束范围，适当地调整所使用的指令寻址范围以适应AT89C2051。程序存储器的加密：AT89C2051可使用对芯片上的两个加密位进行编程（P）或不编程（U）来得到如下表所示的功能：空闲模式：在空闲模式下，CPU保持睡眠状态而所有片内的外设仍保持激活状态，这种方式由软件产生。此时，片内RAM和秘有特殊功能寄存器的内容保持不变。空闲模式可由任何允许的中断请求硬件复位终止。P1.0 和P1.1在不使用外部上拉电阻的情况下应设置为”0”，或者在使用上拉电阻的情况下设置为“1”。应注意的是：在用硬件复位终止空闲模式时，AT89C2051通常从程序停止一直到内部复位获得控制之前的两个机器周期处恢复程序执行。在这种情况下片内硬件禁止对内部RAM的读写，但允许对端口的访问，要消除万事硬件
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