DDR_SDRAM_简介.

1、DDR SDRAM ASIC Course Saeed Bakhshi May 2004 Class presentation based on ISSCC2003 paper: A 1.8V, 700Mb/s/pin, 512Mb DDR-II SDRAM with On-Die Termination and Off-Chip Driver Calibration. Outlines nMemory Evolution nWhat is DDR? nDDR Architecture nHigh Speed Memory Design Considerations nDDR-II Archi

2、tecture nA 1.8V, 700Mb/s/pin, 512Mb DDR-II SDRAM with On-Die Termination and Off-Chip Driver Calibration A paper from: nISSCC 2003; Session 17.8 nSamsung Electronics History of Memory nMemory Evolution 1979 DRAM 1997 SDRAM Next Generation Memories RAMBUS, DDR SDRAM nOnly a few years ago, regular SDR

3、AM was introduced as a proposed replacement for the older FPM and EDO asynchronous DRAM technologies. This was due to the limitations the older memory has when working with systems using higher bus speeds (over 75 MHz). nIn the next couple of years, as system bus speeds increase further, the bell wi

4、ll soon toll on SDRAM itself. nOne of the proposed new standards to replace SDRAM is Double Data Rate SDRAM or DDR SDRAM. What is DDR? nDDR (Double Data Rate) memory is the next generation SDRAM. nLike SDRAM, DDR is synchronous with the system clock. nThe big difference between DDR and SDRAM memory

5、is that DDR reads data on both the rising and falling edges of the clock signal. nSDRAM only carries information on the rising edge of a signal. nBasically this allows the DDR module to transfer data twice as fast as SDRAM. For example, instead of a data rate of 133MHz, DDR memory transfers data at

6、266MHz. nDDR SDRAM also consumes less power, which makes it ideal for notebook computers. nJESD79C is the JEDEC standard for DDR SDRAM specifications. DDR Terminology NameClock Freq.Data Rate DDR200100 MHZ200 MHZ DDR266133 MHZ266 MHZ DDR333167 MHZ300 MHZ DDR400200 MHZ400 MHZ DDR Architecture nThe DD

7、R SDRAM uses a double data rate architecture to achieve high speed operation. nThe double data rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. nA single read or write access for the DDR SDRAM consists

8、 of : Single 2n-bit wide data, in one clock cycle is transferred at the internal DRAM core. Two corresponding n-bit wide data, in two-half clock cycle, are transferred at the I/O pins. DDR Architecture DDR Architecture nData Input Sampling DIND : Input data after Din buffer PE : Pulse generated by t

9、he rising edge of DQS PO : Pulse generated by the falling edge of DQS PCK : Internal Pulse generated by the rising edge of CLK DDR Architecture nOutput Driver Voltage mode push-pull driver ; small rON DDR Architecture nSSTL stands for Series Stub Terminated Logic and has been defined and standardize

10、d within JEDEC. nSeries resistors are incorporated in the SSTL signaling technology for main memory applications. nThese resistors can be very effective in dissipating any reflected wave energy traveling along the module traces and isolating the module stubs from the main memory bus. nProper termina

11、tion of the bus transmission lines, reducing signal reflections. nThe result is improved signal quality, higher clock frequencies, and lower EMI emissions. nSSTL inputs are typically a differential pair common source amplifier with one input tied to the VTT reference. This type of circuit provides e

12、xcellent gain and bandwidth. High Speed Memory Design Considerations nThe Signal integrity is an challenging issue in High speed design. nThe following effects are more important in High Speed Design and can cause data corruption. Reflection Crosstalk and interference SSN (simultaneously switching n

13、oise) nFollowing solutions are employed to improve signal integrity. On die Termination (ODT) Off chip Driver Calibration (OCD) On die Decoupling DDR II nIn JEDEC, DDR-II targeting 667Mb/s/pin is being defined as an extension of DDR. Interface is defined at VDDQ=1.8V. SSTL bus structure has been mod

14、ified for higher data rate. ODT (On Die Termination) is employed for better signal integrity. nDDR2 SDRAM introduces features and functions that go beyond the DDR SDRAM specification and enable DDR2 to operate at data rates of 400 MHz, 533 MHz, 667 MHz, and above. DDR II nNormal DDR limitations at h

15、igher frequencies: Signal integrity Power Consumption nDDR2 Addresses these challenges by: Operating voltage is reduced from 2.5V to 1.8V Reduced core operating frequency Core frequency = 1/2 the I/O frequency nSpecial New Features: 4-bit pre-fetch On-die termination Off-chip driver calibration DDR

16、Evolution DDR and DDR-II DDR-II Architecture 4-bit Pre-fetch nSingle Data SDRAM nIn most DRAMs, the core and the I/O logic are running at the same frequency. In SDRAM each output buffer can relase a single bit per clock cycle. nDDR (I) nIn DDR, every I/O buffer can output two bits per clock cycle. E

17、ach read command will transfer two bits from the array into the DQ. Since the data are fetched from the array before they are released, the memory parlance describes this as prefetch of 2. The simplest way to conceptualize this is to use two separate data lines from the primary sense amps to the I/O

18、 buffers. The DQs are then outputting the data in a time multiplexed manner, meaning one bit at a time on the same output line The easy way to do this is to collect the two bits in two separate pipeline stages and then release them in the order of the queue on the rising and the falling edge of the

19、clock. Because two bits are released to the bus per pin and clock cycle, the protocol used is called double data rate or DDR. 4-bit Pre-fetch nDDR2 SDRAM achieves high-speed operation by 4-bit prefetch architecture. In 4-bit prefetch architecture, DDR2 SDRAM can read/write 4 times the amount of data

20、 as an external bus from/to the memory cell array for every clock, and can be operated 4 times faster than the internal bus operation frequency. ODT ( On-die termination ) nOn-die termination (ODT) has been added to the DDR2 data signals to improve signal integrity in the system. nThe termination va

21、lue of RTT is the Thevinen equivalent of the resistors that terminate the DQ inputs to VssQ and VDDQ. nAn ODT pin is added to the DRAM so the system can turn the termination on and off as needed. ODT (On Die Termination) ODT (On Die Termination) OCD( Off Chip Driver Calibration) nIt is true that low

22、er voltage swings enable higher frequencies but after a certain point, the ramping of the voltages will show a significant skew. The skew can be reduced by increased drive strength, however, with the drawback of a voltage overshoot / undershoot at the rising and falling edges, respectively. nOne add

23、itional problem with high frequency signaling is the phenomenon of trace delays. The solution in DDR was to add clock forwarding in form of a simple data strobe. DDR II takes things further by introducing a bidirectional, differential I/O buffer strobe consisting of DQS and /DQS as pull-up and pull-

24、down signals. Differential means that the two signals are measured against each other instead of using a simple strobe signal and a reference point. In theory the pull-up and pull-down signals should be mirror-symmetric to each other but reality shows otherwise. OCD( Off Chip Driver Calibration) nOn

25、e way to solve the problem is to use Off-Chip Driver calibration (OCD calibration) where both parts of the differential strobes are calibrated against each other and against the DQ signal. nThrough this sort of calibration, the ramping voltages are optimized for the buffer impedances to reduce over

26、and undershooting at the rising and falling edges. nWithout OCD calibration, the DRAM has a nominal output driver strength of 18 ohms +30% and a pull-up and pulldown mismatch of up to 4 ohms. nUsing OCD calibration, a system can reduce the pull-up and pull-down mismatch and target the output driver

27、at 18 ohms to optimize the signal integrity. OCD( Off Chip Driver Calibration) DDR, DDR2 Comparison Table A 1.8V, 700Mb/s/pin, 512Mb DDR-II SDRAM with On-Die Termination and Off-Chip Driver Calibration C. Yoo, K. Kyung, G. Han, K. Lim, H. Lee, J. Chai, N. Heo, G. Byun, D. Lee, H. Choi, H. Choi, C. K

28、im, S. Cho Samsung Electronics, Hwa-Sung, Korea Abstract: A 1.8V 700Mb/s/pin 512Mb DDR SDRAM is JEDEC standard compliant With the hierarchical I/O line and local sensing. For signal integrity at 533Mb/s, off-chip driver calibration and on-die termination are employed. ISSCC 2003; Session17; SRAM and

29、 DRAM Memory Contents nIntroduction nData Path Architecture Hierarchical I/O with Half-Vcc Precharge nSignal Integrity (SI) Improvement Off-Chip Driver (OCD) Calibration On-Die Termination (ODT) nConclusion Introduction nHigh Performance DRAM Trend Fast Access Time High Data Rate Low Power Consumpti

30、on n512M SDRAM with Improved Performance Fast Access time by employing Hierarchical I/O On-die termination & off-chip driver calibration : nsufficient signal integrity for 533Mbps Low voltage operation : 1.8V CHIP Architecture Data Path Architecture nHierarchical I/O with Half-VCC Precharge During read, the loading of GIO lines is decoupled from LIO lines, resulting i