微电子技术 全真模拟试卷（Microelectronic technology simulation test）

1、微电子技术 全真模拟试卷（Microelectronic technology simulation test）This article is contributed by caozhe815DOC documents may experience poor browsing on the WAP side. It is recommended that you first select TXT, or download the source file to the local view.Microelectronic technology simulation test1 terms: an

2、alog integrated circuits, digital integrated circuits, intrinsic semiconductors, intrinsic carriers, equivalent circuit models. Digital integrated circuit: circuit that performs operations entirely in binary logic for transmitting and processing digital signals. Analog integrated circuit: a circuit

3、for acquiring, transmitting, processing and converting analog quantities. Intrinsic semiconductor: pure semiconductor material without impurities and defects; pure semiconductors have very poor electrical conductivity. Intrinsic carriers: carriers (electrons and holes) in intrinsic semiconductors. T

4、hat is not the carrier produced by doping. That is to say, the intrinsic carrier is composed of thermal excitation of intrinsic excitation produced, which is the valence electrons to the conduction band produced from the valence band; they are produced in pairs, so the concentration of electrons and

5、 holes are always equal. Equivalent circuit model: equivalent circuit - a circuit model that represents the electrical characteristics of solid state electronic devices. 2 the relation between intrinsic carrier concentration and temperature of semiconductor materials is given by the formulaNi = pi =

6、 AT3/2E.E g / 2 KTRules and main characteristics of the 3 development of microelectronic technology development law: Moores law, namely the development of integrated circuit technology: every three years to upgrade the generation and integration of every three years over two, width of about 30% smal

7、ler, the logic circuit (represented by CPU) the working frequency is increased by about 30%. Main features: smaller size (minimum gate length or width MOS) chip size increasing (die size) the number of transistors on a single chip clock speed more faster and more and more low voltage power supply wi

8、ring layer of more and more I/O lead more and more 4 brief description of integrated circuits are divided into several scale class. SSI (Small Scale IC): 109 5: in the current crowding effect at the edge of the emitter, the emitter potential is higher in the center of the lower potential (or even 0)

9、; then, causing the emitter surface on the voltage difference (voltage emitter around the edges of the high and low voltage at the center), so that the injected current density is also different the current density of the emitter around the edge of the emitted junction, the current density is at the

10、 center of the 0, the emitter current basically focused on the surrounding emitter junction of a circle, this is the edge crowding effect of emitter current. The measures are as follows: limiting the current capacity so as not to have the effect of the current collector; improving the doping concent

11、ration of base region to decrease the base resistance; and increasing the emitter perimeter / area ratio. 6 illustrates the NMOS enhancement transistor structure and the conductive channel formation process.The MOS tube, consisting of a p type substrate and two high concentration n diffusion regions

12、, is called the N channel MOS tube, which forms a n type conducting channel at two high concentration n diffusion intervals.1/6N channel enhancement mode MOS tube must exert positive bias at the gate and only the gate source voltage is greater than the threshold voltage when the catheter should forw

13、ard bias is applied on the gate electrode, and only the gate source voltage is larger than the threshold voltage is MOS N channel channel produce tube. In the P type silicon substrate with a low doping level on p-type silicon substrate, two high doping concentration of the N+ region, and the metal a

14、luminum and aluminum metal leads to two leads to the two electrodes, respectively the drain and source s D. Then in the semiconductor surface covered with a thin layer of silica and then covered with a thin layer of silicon dioxide on the surface of the semiconductor (SiO2) insulating layer, the ins

15、ulating layer in the drain - source and fitted with an insulating layer of aluminum source and fitted with an aluminum electrode between the electrodes, as the gate of G. An electrode B is also introduced on the substrate, which also leads to an electrode on the substrate to form a N channel enhance

16、d MOS tube. The gate - source voltage vGS increases, P attracted to the electronic substrate surface layer on the increase, when the vGS reaches a certain value to attract to reach a certain value, the electrons in the P substrate surface near the gate to form a thin layer of type N, and two N+ conn

17、ected area is communicated in the drain - source formed between N type conductive channel. 7 draw the vertical structure and transverse structure of the bipolar transistor. Sketch the vertical structure and transverse structure of the bipolar transistor and mark the names of each part.8 briefly desc

18、ribes the main process of photolithography process, and briefly describes the main process of lithography process. Lithography process consists of coating, exposure, development and other steps, a, cleaning: SiO2 surface drying layer surface drying. B, the positive photoresist coating: light in the

19、area when developing easy to remove positive photoresist materials is a typical ortho quinones azido photoresist by the light of the regional development in the easy removal of positive photoresist material is a typical ortho quinones azido compounds. By the light of the photoresist was retained in

20、the region after developing the unexposed glue removed negative photoresist material negative resist negative photoresist material: typical photoresist by the light of the region after developing is to keep the material is polyvinyl alcohol cinnamic acid ester. C, pre bake (soft bake), pre exposure

21、bake (or soft bake), so that the solvent in the photoresist to evaporate, so that the film into a solid state of the film, so that the film into a solid state of the film. D and exposure exposure are chemical reactions of photoresist films irradiated by light. The exposure is affected by the photore

22、sist film light chemical reaction e, developing the silicon wafer in the developer has been exposed in the film in a latent image display. For negative rubber, the exposed silicon wafer is immersed in the developer, and the photoresist which is not exposed to the photoresist is dissolved in the deve

23、loping process. That part of the photoresist is dissolved in the development of F, hard film lithography, after development, must be baking again, the residual solvent content of the glue to the minimum, also known as hard bake. That must be baked again,The residual solvent content in the gum is red

24、uced to a minimum, and the film after development becomes hardened and adheres better to silica. The film after developing further harden and adhesion of silica and better g) the main effect of corrosion is the main function by exposing photoresist micro graphics exposed part of lower material is re

25、moved by etching the exposure of photoresist micro graphics exposed part of lower material removal.2/6H) the mission to remove photoresist from etching has been completed, and the photoresist must be removed. When the etching has been completed, the mission of etching the resist has been completed a

26、nd the photoresist must be removed. 9 the diffusion methods used in semiconductor doping process are briefly described. The diffusion methods used in semiconductor doping process are briefly described. A liquid source is diffused to protect a gas (such as nitrogen) through a liquid source containing

27、 impurities to carry impurity vapors into a diffusion furnace at high temperature. At high temperature, through the impurity containing liquid source, the impurity vapor is carried into the diffusion furnace under high temperature. The impurity steam decomposes and reacts with silicon to form impuri

28、ty atoms. The impurity atoms diffuse through the surface of silicon wafer to the interior. The impurity atoms are generated by reacting with silicon, and the impurity atoms diffuse through the surface of the silicon chip to the interior. Two, the sheet source diffused sheet source is a solid diffusi

29、on source similar to that of the silicon wafer. Flake source is a silicon wafer with the same solid diffusion source will be the first source and silicon chip and inserted in the groove of the quartz boat and then spread at a certain temperature, the source and silicon chip and is inserted in the gr

30、oove of the quartz boat, impurity steam and silicon reaction of impurity atom diffuses. This step is called pre deposition. Remove the chip, then bake with oxygen and bake with oxygen to improve the surface condition of the wafer. Then, at a higher temperature for re diffusion. Then, at higher tempe

31、rature, three of the solid solid diffusion is the solid impurity of the silicon substrate, and the impurity diffuses from the solid film to the substrate. Impurity source is solid solid diffusion film on silicon substrate, the effect of impurities from the solid film diffusion into the substrate to

32、10 briefly in the process of plane lateral diffusion of the integrated circuit a brief description of the influence of the transverse diffusion process of planar integrated circuit. The influence of transverse diffusion: the width of the actual diffusion layer is larger than the width of the oxide w

33、indow, so that the width of the actual diffusion layer is larger than the width of the oxide window, and the final junction surface is not entirely planar. Its influence: device breakdown voltage, device breakdown voltage. The distance between windows 11 explains the electromigration phenomenon of m

34、etals and the problem of aluminum silicon interaction, and explains how to solve the electromigration phenomenon and the interaction between aluminum and silicon. Electromigration in metal aluminum is a polycrystalline structure, aluminum metal atom packing aluminum metal atoms at the high potential

35、 accumulation at the high potential, the formation of hillock and whisker whisker, leading to the adjacent metal wire short circuit; and the low potential atomic shortage and the formation of voids caused by open circuit. In the low potential atomic shortage and the formation of voids leads to open

36、aluminum silicon solubility in aluminum silicon solubility, to penetrate inside the silicon into silicon, easy to form spikes, make a short circuit for shallow junctions,Relatively strict, for shallow heavy. In order to solve the phenomena: (1) the need for aluminum film structure design for structu

37、re of aluminum film for design; (2) the use of Al-Cu alloy and Al-Si Si-Cu alloy (3) multi-layer structure (such as: Al/Ti/Al, Al-CrAl7-Al) in order to solve the spike phenomenon (1) using Al-Si or Al-Si-Cu (2) using aluminium alloy doped polysilicon double layer metal structure can provide silicon

38、atoms dissolved in aluminum needed. The doped polysilicon double layer metallization structure can provide the silicon atoms (3) needed for the dissolution of aluminum, and adopts an aluminum barrier structure. A thin layer of metal is deposited between silicon and aluminum and a thin layer of metal

39、 is deposited between the silicon and aluminum. 12 a brief description of the MOSFET common isolation process and how to overcome the parasitic MOS tube effect. Is the field parasitic MOS open voltage is higher than the source voltage 10V, MOSFET is not conductive. Method: increasing the doping conc

40、entration in the field and increasing the doping concentration in the field. Increasing the oxide thickness of the field zone. 13 N well CMOS process, N channel MOS transistor preparation process schematic diagram, brief description of the main process, brief description of the main process. (1) the

41、rmal oxidation (2) lithography (3) etching (4) N type ion implantation (5) annealing (6) high temperature well propulsion3/614 If function f = AB + C, try NMOS to implement the logic circuit, draw the corresponding layout, and analyze its logical relationship and working principle.Principle of work.

42、 15 programmable erasable ROM unit MNOS (EEPROM) structure and principle, explains how to read and write data and erase data.4/6The answer is on the internet. When there is no electron injection in the floating gate, the electrons in the floating gate run up to the upper layer and the lower layer is

43、 void when the gate voltage is added. Because of the induction, it attracts electrons and turns on the channel. If there is an injection of electrons in the floating gate, i.e., the threshold voltage of the enlarged tube, the channel is in a closed state. Thus, the switch function is achieved.As sho

44、wn in Figure 2, this is the process of writing the EPROM at the drain plus high voltage, and the electrons flow from the source to the drain channel fully open. Under the action of high pressure, the tensile force of the electron is strengthened, and the energy makes the temperature of the electron

45、rise extremely and become electron (hot). This is almost not affected by the vibration caused by the electron scattering effect of the atom, in a controlled gate applied pressure, thermal electrons to SiO2 over the barrier, injected into the floating gate. In the absence of any external force, the e

46、lectron will hold well. When electrons need to be removed, ultraviolet radiation is applied to give the electrons enough energy to escape the floating grid.The EEPROM write process takes advantage of the tunneling effect, i.e., electrons with less energy than the energy barrier can cross the barrier

47、 and reach the other side. Quantum mechanics holds that the size of the physics is in accordance with the electron free path. At that time, the electrons will exhibit volatility, which means that the object should be small enough. In terms of the PN junction, when the impurity concentration of P and

48、 N reaches a certain level and the space charge is very small, the electron will migrate due to the tunneling effect. The energy of an electron is at a certain level. The range allowed is called the band, and the lower band is called the valence band, and the higher band is called the conduction ban

49、d.When electrons reach the higher conduction band, they can move freely between atoms, which is current. The EEPROM write process, shown in Figure 3, according to the tunneling effect, the SiO2 that surrounds the floating gate must be extremely thin to reduce the barrier. The source drain is grounde

50、d and is in the conduction state. A high voltage above the threshold voltage is applied on the control gate to reduce electric field action and to attract electrons through.5/6To achieve the requirement to eliminate electrons, EEPROM is also achieved by tunneling. As shown in Figure 4, the drain is

51、charged high, the control grid is 0V, and the pulling direction is reversed, and the electrons are pulled out of the floating grid. This action, if the control is not good, there will be the result of elimination. 16 please draw a circuit diagram of the SRAM (static random access memory) unit made u

52、p of MOS circuits, and briefly describe how to read and write data.Write operation. Write operation. Turned on, the selected: add a positive voltage to a word line word pulse, T2, T3 is turned on, the selected unit that is selected: add a positive voltage to a word line word pulse, voltage drop to g

53、round potential (if write 0, no matter what state it is. Only need to write 0 bit line voltage down to BS0 potential (and if written, regardless of the original is what kind of state, only need to write the negative bit line voltage pulse) by conducting T, the potential force conduction node A is equal to the earth potential, negative voltage a pulse) through conducting T2 tube, forcing the node A is equal to the earth potential, low B and high A, T1, and T0 pipe cut-off tube. The tube is cut off and the T tube is connected. Down to the ground, tube to node B, B, A if write 1, o