EDA用VHDL语言设计一个2-4译码器

1、2-4 译码器LIBRARY IEEE;USEdecoder 2 _4 ISPORT( a:IN STD_LOGIC_VECTOR(1 DOWNTO 0);s:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END decoder2_4;ARCHITECTURE Behavioral OF decoder2 _4_t ISBEGINPROCESS(sel)BEGINCASE a ISWHEN 00=ssssssssss=ZEND CASE;END PROCESS;END Brhavioral;100 进制加法计数器LIBRARY IEEE;USEcounter ISPORT(

2、clk,en,load,rst:IN STD_LOGICd;IN STD_LOGIC_VECTOR(6 DOWNTO 0);q: OUT STD_LOGIC_VECTOR(6DOWNTO 0): END counter 100;ARCHTECTURE Behavioral OF counter 100 IS signal qtemp:STD_LOGIC_VECTOR(6 DOWNTO 0);BEGIN PROCESS(clk,d,en,load,rst)BEGINIF rst= 1 THEN qtemp= ” 00000000”;IF en=1 THENIF load= 1 THEN qtem

3、p=d,ELSIF qtemp=” 1100011” THEN qtemp= ” 00000000”;ELSIF qtemp=qtemp+ 1;END IF;END IF;END IF;END PROCESS;q=qtemp;END Behavioral;8 位从高至低串入串出移位寄存器LIBRARY IEEE;USEISPORT( d,clk:IN STD_LOGIC;q:OUT STD_LOGIC);END d ;ARCHITECTURE Behavioral OF ISsignal qtemp:STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINPROCESS(d,clk

4、)BEGINIF rising-edge(clk) THENq=dtemp(0);dtemp=d&dtemp(7 DOWNTO 1);END IF;END PROCESS;END Behavioral;状态机LIBRARY IEEE;USEfsm ISPORT(tin,clk:IN STD_LOGIC;yout:OUT STD_LOGIC_VECTOR(1DOWNTO 0);END fsm;ARCHITECTURE Behavioral OF fsm ISTYPE state-type IS (S0,S1,S2)signal state,next_state:state_type;BEGINSYNC_PROC:PROCESS(clk)BEGINIF rising_edge(clk) THENstate yout yout youtyout=” zz” ;END LAST;END PROCESS;NEXT_STATE_DECODE:PROCESS(state,tin)BEGINnext_statenext_state next_stateIF tin= 0 THEN next_state