出租车计价器课程设计报告 英文版

1、engineering project management(2) course paper title: specialty：taxi meter class：h1303 name：han tong li xinhao student id：1310920516 1310920517 catalogcatalog 一、一、introductionintroduction.1 1 二、二、overalloverall designdesign schemescheme.1 1 （一）（一） 、s softwareoftware andand hardwarehardware flowflow

2、chartchart.2 2 （二）（二） 、s sourceource programprogram designdesign andand hardwarehardware introductionintroduction.5 5 2.12.1 80868086 minimumminimum systemsystem modulemodule .5 5 2.22.2 chipchip 8255a8255a .6 6 2.32.3 chipchip 82538253 .7 7 2.4programmable2.4programmable controlcontrol chipchip 825

3、9a8259a .8 8 （三）（三） 、p problemsroblems encounteredencountered.9 9 三、三、summarysummary andand experienceexperience.1010 四、四、referencereference：.1010 appendixappendix.1111 0 一、introduction taximeter is both passengers and drivers of the trade standards, it is an important symbol of the development of t

4、he taxi industry, is in a taxi is the most important tool. it is related to the interests of the parties to the transaction. with good performance of the meter whether is very necessary for the majority of taxi drivers or passengers. therefore, the automobile valuation of is an application value. ou

5、r country in the 1970s began to taxi, but then the billing system mostly imported not only accurate, price is also very expensive. with the deepening of reform and opening up, the development momentum of the taxi industry has been very prominent, the domestic machinery manufacturers have launched do

6、mestic meter. taxi valuation functions from at the beginning of the show only away (the driver himself pricing, calculated after four homes in five), to independent billing, and now can play an invoice and a voice prompt, according to time independent changes in price function. with the development

7、of urban tourism, the taxi industry has become the citys window, a symbol of the civilization of a city degree. with the development of the taxi industry, the taxi is an important 1 part of urban traffic, starting from strengthening the industry management and reduce disputes of driver and passenger

8、, with good performance meter to taxi drivers and passengers are very necessary. we design the 8086 based controller, to a44e hall sensor location, on the taxi multifunctional pricing design, the output of the 8 digital tube display. 二、overall design scheme by 8253 as timer / counter, motor speed an

9、d measurement of motor speed control; 8255 as input and output interface, control digital tube display after the start mileage (after the decimal point from two effective value). hardware connection description: based on the dc motor controller, a motor speed measurement circuit is added. b the 8255

10、 port as digital tube stroke code driven; the low four bits of a c port as the segment code control, showing the actual mileage. at the same time, also for the keyboard output column scan code; pc6 and pc7 input line scan code for the key identification, procedure using only the pc6 four buttons, wh

11、ich is defined as follows: 2 x1: start / stop button; x2: accelerator key, and x3, x4 key combination to use; x3: + button; x4: - key. a mouth only uses the pa0, the output pwm pulse signal, by driving the motor, the output voltage is proportional to the duty cycle of the pwm pulse. the number of re

12、volutions of the motor, through the hall element transformation for pulse number, into the 8253 passage 2, counting, speed is converted to mileage, the smallest unit is 0.01 km, send the recorded cpu. the results by the digital tube display. 3 （一）（一） 、software and hardware flow chart ad7 ad0 ad4 ad5

13、 ad1 ad2 ad3 ad6 d0 34 d1 33 d2 32 d3 31 d4 30 d5 29 d6 28 d7 27 rd 5 wr 36 a0 9 a1 8 reset 35 cs 6 pa0 4 pa1 3 pa2 2 pa3 1 pa4 40 pa5 39 pa6 38 pa7 37 pb0 18 pb1 19 pb2 20 pb3 21 pb4 22 pb5 23 pb6 24 pb7 25 pc0 14 pc1 15 pc2 16 pc3 17 pc4 13 pc5 12 pc6 11 pc7 10 u2 8255a ad0.15 ready 22 intr 18 nmi

14、 17 reset 21 clk 19 mn/mx 33 hold/gt1 31 hlda/gt0 30 a16.19 m/io/s0 28 ale/qs0 25 dt/r/s1 27 inta/qs1 24 test 23 bhe 34 den/s2 26 rd 32 wr/lock 29 u1 8086 ir0 18 ir1 19 ir2 20 ir3 21 ir4 22 ir5 23 ir6 24 ir7 25 int 17 inta 26 cs 1 wr 2 rd 3 a0 27 sp/en 16 d0.7 cas0.2 u3 8259 d0 8 d1 7 d2 6 d3 5 d4 4

15、 d5 3 d6 2 d7 1 rd 22 wr 23 a0 19 a1 20 cs 21 clk0 9 gate0 11 out0 10 clk1 15 gate1 14 out1 13 clk2 18 gate2 16 out2 17 u4 8253a 1b 1 2b 2 3b 3 4b 4 5b 5 6b 6 7b 7 8b 8 1c 18 2c 17 3c 16 4c 15 5c 14 6c 13 7c 12 8c 11 com 10 u5 uln2803 a 1 b 2 c 3 e1 6 e2 4 e3 5 y0 15 y1 14 y2 13 y3 12 y4 11 y5 10 y6

16、 9 y7 7 u6 74als138 1 2 3 u7:a 74s09 main program flow 4 n y n y nnn yyy iro interrupt processing flow chart ir7 interrupt handler stream modify 8, f number interrupt vector, point to ir7, iro interrupt handler write 8259 ocw1 open ir7, iro interrupt initialization 8253, cho to take the way 2, ch2 t

17、o take the way 3, are used to write a low 8, after writing the 8 high, binary count bcd code of the compression code of the mileage soeed converted into a non compressed bcd code, memory display buffer write 8253 channel 0 and 2 initial values for 609 and 50 off motor, pa0=0 open the keyboard port 延

18、时，去抖动 call display subroutine is there a key press? line scanning method to identify keys, ah memory scan code is the accelerator key? the highest position of ah 1, d7=1 is the start / stop button is + key ?accelerati on? accelerati on?吗？ mileage =0 rev 动 set to stopduty cycle +1 duty cycle +10 duty

19、 cycle - 1 duty cycle -10 循环 5 n y n y n y display subroutine flow chart n y n y （二） 、source program design and hardware introduction save the scene, ax into the stack is the starting state? high level time - 1=0? reload high level time, pa0=0 pwm timing - 1=0? reload pwm timing, pa0=1 resume the sc

20、ene, the end of the interruption interrupt return save the scene, ax into the stack open interrupt, allow iro to speed the interrupt take out the current number of compressed bcd code low byte +1, decimal number high byte +0+ carry, decimal modulation save the results to the mileage speed resume the

21、 scene, the end of the interruption interrupt return save the field, register the stack bx to display si code table, pointing to the buffer take out a byte display data, converted to display code display second digits 据吗数据 吗？ display the decimal point, the display code 80h or 4 bit display code off

22、display, restore the scene return 6 interrupt routine mileage counter interrupt routine whenever hall sensor outputs a low level signal makes a break, when the mileage counter on the mileage pulse meter over 1000 times, enter the mileage count the interrupt service program, mileage variables plus on

23、e. the main function of the total amount also correspondingly changes. interrupt routine in the middle of the pending interrupt program, 1ms each generate an interrupt, the current mileage value into a variable cache, every 5 minutes will be variable cache value and current mileage values compared w

24、hen stop the car, the hall sensor for 5 minutes without signal output, current mileage value cache and variable quantity of the same value, then enter the waiting time, every 5 minutes to remember a price. display program procedures for the use of timer 1ms per generated once interrupted, the corres

25、ponding variable set, light a digital tube display a data display, recycling within the main function, realize the dynamic scan display, also according to the afterglow of the human eye and the persistence of digital tube, you can achieve the display. keyboard program keyboard using the way of inqui

26、ry, in the main program, when no key is pressed, the cycle of the main program, once the right button is pressed, they turn to the corresponding subroutine to deal with the end of the treatment to return. 2.1 8086minimum system module 1、8086cpu constitute the system block diagram： 7 2.2 chip 8255a 1

27、、 the role of 8255a in this experiment, we use 8255a to transfer the digital quantity of analog quantity to cpu., and 8255 to control the work of adc0809 by way of inquiry work.8086 sends control signals through 8255 to seven led displays. 2、 function analysis of 8255a 8255a is parallel programming

28、interface, can according to external conditions (i / o devices need to signal lines and it can provide the state line) to enable the various interface circuit.8255a internal three data port, namely port a, b, c a port port have three modes: mode 0, type 1 and type 2, and port b can only work in mode

29、 0 or 1, and c usually as contact signal is used. in this experiment, the control word design 80h, initialization 8255, the port b, c as output. in three kinds of work, this design uses only mode 0, 0 is the basic input / output, in this way, three ports can by the program specified input / out of t

30、he way, but not both as input as output, did not provide a fixed contact network signal c divided into two four, four high and low four bits can be respectively arranged for input or output. 3、technical parameters of 8255a 8255a pin signal 8 1）connected to a peripheral device. pa7pa0：a port data sig

31、nal line； pb7pb0：b port data signal line； pc7pc0：cport data signal line； 2）connected to cpu reset: the reset signal. when this signal comes, all registers are cleared. at the same time three data ports are automatically set to the input port. d7d0: they are connected to the 8255a data line and the s

32、ystem bus. cs: chip select signal. in the system, general according to all the interface chip to allocate at low address (such as the a5, a4, a3) composed of various chip select code. when the address consists of a low level, on 8255a is selected. only when available, the signal read and write to th

33、e 8255 for reading and writing. rd: read the signal. when this signal is valid, the cpu can read data from the 8255a. wr: write a signal. when this signal is valid, cpu can write data to the 8255a. a0, a1: port selection signal.8255a has 3 data ports and 1 control ports, a total of 4 ports: a1, a0 i

34、s 00, select the a port; a1, a0 is 01, select the b port; select signal active, low cs:chip; a0:, address signal. a1 pc jp52: port; pb jp53: port; pa jp56: port. 9 a1, a0 is 10, select the c port; a1, a0 11, select the control port. 4、 8255a mode control word 8255a control word has two kinds: one is

35、 the way to select the control word, the other is the c port to press the position / reset control word mode select control word figure 1 8255a control table c port position / reset control word chart2 8255a set / control table 2.3 chip 8253 1、8253 function analysis nmos intel8253 process is made of

36、 programmable counter / timer, there are several types of chip models, external pins and functions are compatible, but the work of the maximum count rate is different, such as 8253 (2.6mhz), 8253-5 (5mhz) chip 8253 has three counters, were to become counter 0, counters 1 and 2, their bodies are comp

37、letely the same. input and output of each counter decided to to set in control register the control word, between each other to work completely independently. each counter by three of the pins and the external contact and a clock clk input and a gating signal input end of the gate, another output te

38、rminal out. each internal counter is a 8 bits of the control register and a 16 bit count initial value register cr, a count execution component ce and an output latch application 10 actuator is actually a 16 bit subtract counters, the initial value is the value of the initial value register, and the

39、 initial value register value is set by the program. the output latch latch value is set by the program. the output latch ol is used to latch the count execution component ce content, so that the cpu can be this read operation. incidentally, cr, ce and ol are 16 bit register, but can also for 8-bit

40、registers to use 18253 role 2、8253 pin signal 2.4 programmable control chip 8259a principle of 8259a a piece of 8959a eight interrupt request line ir0ir78259a by the operating system initialization, you can receive interrupt signal.8259a from the ir request line an interrupt signal, each request lin

41、e a trigger to keep the request signal, so as to form the interrupt request register (irr). at the same time, if the interrupt request signal line not be shielded, 8259a to cpu issued int signal, an interrupt request. at this time, if the cpu is in the allowed the interrupt status, the cpu will send

42、 inta signals to the 8259a enter the interrupt response time. if there is more than one letter of request , arriving at the same time, 8259a priority circuit will be priority selection for each request, the request of the highest priority in the interrupt response cycle and sent to interrupt service

43、 register (isr) will it set, and reset the irr of the corresponding bit. then cpu again send a inta pulse to the 8259a, start another interrupt the corresponding period.8259a in the corresponding period to the data bus d0-d7 input an interrupt vector cpu according to the vector of x4 value can be fr

44、om interrupt entry cs：chip select signal, active low; a1, a0: address signal; 11 address table (idt) remove the interrupt service program entry address into the interrupt service procedures. while 8259a if the work in the automatic end interrupt (aeoi) mode automatically so that the corresponding bi

45、t in the isr reset, or need to issue a eoi command to reset the isr. in pc-xt/at old - fashioned generally use a piece of 8259a interrupt request signal. in most modern pc, usually with two 8259a as level even. the piece is master slave, due to master an interrupt request line needs to be connected

46、to the slave int foot, with the actual use of the external interrupt number is 15 (8 * 2 - 1). 8259a structure 1, data bus buffer -d7 d0 data bus buffer for the three state, two-way, 8 bit registers, the data line d7 d0 and cpu system bus connection, constitute the cpu and 8259a between the transmis

47、sion of information channel. 2, read / write control logic -wr/wd the read / write control logic is used to receive the read / write control signal and the port address selection signal of the cpu system bus, which is used to control the read / write operation of the 8259a internal register. 3, casc

48、ade buffer / comparator 12 8259a can operate on a single, also can work in a plurality of cascade, cascade hardware connection as shown in figure 6.10. cascade buffer / comparator to provide multi chip 8259a management and selection function, the main chip, for the rest of the from the film. 4, inte

49、rrupt control logic interrupt control logic to follow the programmed management approach to interrupt, responsible for on-chip components for sending a control signal to the and sent to a cpu interrupt request signal int and receive loopback cpu interrupt response of inta signals, control 8259a disr

50、uption into state management. 5, interrupt request register (request register interrupt, irr) irr is an 8-bit registers, used to record the external interrupt request. which d7 to d0 respectively and external interrupt request signal ir7 ir0 corresponds, when iri (i = 0 7) request (level or edge tri

51、ggered), irr the corresponding bit di is set to 1, in response to interrupts inta signals effectively di is cleared. 6, interrupt service register (service register interrupt, isr) di impulse impulse response (iri isr is an 8-bit registers, used to record the current cpu is service interrupt flag. w

52、hen the external interrupt i = 0 7) requested by the cpu to enter service by the cpu to the first interrupt response inta isr in the corresponding bit di (i = 0 7) is set to 1, and the isr is restored to the throne the 8259a interrupt closing decision. if the definition for automatic closing, by the

53、 cpu of the second interrupt response inta along will reset to 0; if the definition is not automatically end, the cpu sends to the end of interrupt command in its reset . 13 7, interrupt mask register (mask register interrupt, imr) imr is an 8-bit registers, used to store ir7 ir0 interrupt mask flag

54、. its eight mask bit d7 to d0 and external interrupt request ir7 ir0 corresponding, for controlling iri request is allowed to enter. when the imr di bit is 1, corresponding to the iri request forbidden; when the imr di bit is 0, then allow a corresponding interrupt request to enter. it can be set by

55、 software or clear. by programming setting mask word, can change the original priority level. see appendix for program code three, summary and experience as a automations big three students, i think doing computer programming is very meaningful, and it is very necessary. during the university time h

56、as passed, most of our contact is professional class. we master english in the classroom is only theoretical knowledge of professional courses, how to exercise our ability to practice? how to apply what we learn professional basic course of theory knowledge to practice it? i want to do a similar cou

57、rse design is for us to provide a good platform for practice. the importance to learn professional course curriculum design in the curriculum design process, i feel the deepest undoubtedly access to a large number of design data. in order to make their design more perfect, access to this information

58、 is very necessary, but also essential. secondly, in this design, we use the previously learned knowledge, such as: assembly language, analog and digital circuit knowledge. although in the past have never been alone used them, but in the learning process with a problem i find efficiency is very high

59、, this is me to do the curriculum design of a harvest. on the other, the curriculum design, let me feel the team. in the team, i our mutual cooperation, on the course design, which is crucial, lack of every person will have an impact on our design. also to be thanked 14 the teacher when we meet with

60、 difficulties, giving our suggestions and encouragement. end of the two weeks of the course design, but from the middle school to knowledge will let me a lifetime. the results show that the proposed analysis, solve problems and practical ability raise will benefit to me in the future learning, work