数字逻辑设计第六章(6)

1、1HS CO0 0 0 00 1 1 01 0 1 01 1 0 1X Ytruth table for half adderThe sum: HS = XY + XY = X YThe carry-out: CO = XYCO0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1CI X YStruth table for full adderHalf AddersHalf Adders and Full Addersand Full Adders（半加器和全加器（半加器和全加器）6.10 Adders

2、 6.10 Adders （加法器）（加法器）6.10 Adders （加法器）2CO0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1CI X YStruth table for full adderHalf AddersHalf Adders and Full Addersand Full Adders（半加器和全加器（半加器和全加器）CO = XY + XCI + YCISCOXYCIS = X Y CI(Fig. 6-83)X YCO CIS3缺点：运算速度慢，有较大的传输延迟。缺点：运算速度

3、慢，有较大的传输延迟。最大延迟：tADD = tXYCout + (n-2)tCinCout + tCinSX YCO CISX YCO CISX YCO CISX YCO CISC3C2C1C0C4S3S2S1S0X3 Y3X2 Y2X1 Y1X0 Y0=0Iterative CircuitIterative Circuit 提高速度：改变串行结构 Ripple Adders Ripple Adders（串行（串行/ /行波进位加法器）行波进位加法器）4一位全加器： Si = Xi Yi Ci = HSi Ci先行进位法：第第(i +1)位的进位输入信号可由该位以前的各位决定。位的进位输入信

4、号可由该位以前的各位决定。Ci+1 = (XiYi) + (Xi+Yi) Ci= gi + pi Cicarry-generate signalCarry-propagate signalHSiCiXiYiSiX0先行进位逻辑Xi-1Y0Yi-1C0 Ci+1 = XiYi + XiCi + YiCi = XiYi + (Xi+Yi)Ci Carry-Lookahead addersCarry-Lookahead adders（先行进位加法器）（先行进位加法器）5C0 = 0Ci+1 = gi + pi CiC1 = g0+p0C0C2 = g1+p1C1 = g1+p1g0+ p1p0C0

5、C3 = g2+p2C2 = g2+p2g1+ p2p1g0 + p2p1p0C0 C4 = g3+p3C3 = g3+p3g2+ p3p2g1 + p3p2p1g0 + p3p2p1p0C0每一位进位信号的产生只有三级延迟：第第1级：级：gi和和pi的产生；的产生；2, 3级：上述级：上述“与与-或或”表达式表达式。 Carry-Lookahead addersCarry-Lookahead adders（先行进位加法器）（先行进位加法器）6HS0X0Y0S0C0HS1C1X0F1Y0X1Y1S1C0HS2C2X0F2X1X2Y2S2C0Y0Y1Fi为先行进位逻辑HSiCiXiYiSiX0F

6、iXi-1Y0Yi-1C0Ci+1X0FiXiY0YiC0 Carry-Lookahead addersCarry-Lookahead adders（先行进位加法器）（先行进位加法器）7 MSI Adder 74x283 4-bit binary adder using carry-lookahead technique. A 16-bit adder using 74x283s片内超前进位；片内超前进位；片间串行进位。片间串行进位。(Fig. 6-87, 6-88)*Subtractors（减法器）8 D = X Y BI BO = XY + XBI + YBIBO0 0 0 0 00 0

7、1 1 10 1 0 1 00 1 1 0 01 0 0 1 11 0 1 0 11 1 0 0 01 1 1 1 1BI X YDtruth table for full adderFull Subtractor D = X Y BI BO = XY + XBI + YBI 全减器可由全加器实现： S = X Y CICO = XY + XCI + YCI对比全加器：对比全加器：把借位输入、借位输出和减数信号均看作低把借位输入、借位输出和减数信号均看作低电平有效信号，则全减器可由全加器实现。电平有效信号，则全减器可由全加器实现。BO= (X+Y)(X+BI)(Y+BI) = XY + XBI

8、 + YBI*Subtractors（减法器）9逐位求反X0 Y0=1X YCO CISX YBO BIDXn-2 Yn-2Xn-1 Yn-1X YBO BIDX YBO BIDb_L0b_L1b_Ln-2b_Ln-1b_Lnd0dn-2dn-1 n-bit ripple subtractor （n n位串行借位减法器）位串行借位减法器）X YBO BID末位加1*Subtractors（减法器）10 任何任何n n位加法器都可以用做减法器：位加法器都可以用做减法器：加法器( (如如74x283)74x283)Xn-1:0Yn-1:0Sn-1:0CI=0CO加法器( (如如74x283)74x

9、283)Xn-1:0Yn-1:0Dn-1:0BI_L=1BO_L逐位取反MSI Adder Using a four-bit binary parallel adder as a four-bit binary adder/subtracter. 8 value input a+b =a4a3a2a1+b4b3b2b1+0 a-b = a4a3a2a1-b4b3b2b1 = a4a3a2a1+b4b3b2b1+1 1 control input M=0, a+b M=1, a-bMSI Adder A4A3A2A1 A4=a4 ; A3=a3 ; A2=a2 ; A1=a1; B4B3B2B1

10、 M=0, Bi=bi; M=1, Bi=bi; Bi=f(M,bi) =M bi; CI M=0, CI=0; M=1, CI=1; CI=f(M)=M;MSI AdderA4A3A2A1 B4B3B2B1F4 F3 F2 F1COCIe4 e3 e2 e1a4a3a2a114SummarySummary Documentation Standards Circuit timing Propagation Delay Timing Diagram（由定时图判断逻辑函数）（由定时图判断逻辑函数） Decoders: 74x138, 74x139 Encoders: Priority Encode, 74x148 Three-State Devices Multipl