串行扫描显示电路设计---文本资料

1、输入时钟inlck为50Mhz ,经分频为1hz,再进行0F范围计数，计数的结果分 别在seg3-seg1睦8个串行数码管显示；8个数码管受74138译码器的控制；189,190,191,192,193,195,196 , 197串行扫描显示电路设计1 .实验目的1 .通过用VHDL语言设计串形扫描显示电路进一步掌握使用VHDL方法。2 .熟悉使用CPLD/FPGA实验箱的数码管进行显示。2 .实验仪器1. PC机一台2 . KHF-1/KHF-2/KHF-3/KHF-4/KHF-5 CPLD/FPGA 实验开发系统一套。三、实验要求1 .预习串行扫描显示的原理2 .复习教材相关内容。3 .用

2、硬件描述语言进行电路设计。四、实验内容及实验步骤1 .串形扫描显示电路设计原理a,b,c,d,e,f,g, p 段2 .编译。3 .分配管脚。4 .编译。5 .启动下载软件进行下载。五实验代码library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity tcx isport(inclk:in std_logic;outb:out std_logic_vector(7 downto 0);outa:out std_logic_vector(2 downto 0);end tcx;architectu

3、re arch_tcx of tcx issignal ma:std_logic_vector(2 downto 0);signal mb:std_logic_vector(3 downto 0);signal fp:std_logic_vector(24 downto 0);signal f:std_logic;beginprocess(inclk)beginif(inclk'event and inclk='1')thenif fp=24999999 thenfp<="0000000000000000000000000"f<=not

4、f;elsefp<=fp+1;end if;end if;end process;process(f)beginif(f'event and f='1')thenma<=ma+1;mb<=mb+1;end if;end process;outa<=ma;with mb selectoutb<= "10110000"when"0001",-1"11101101"when"0010",-2"11111001"when"0011"

5、;,-3"10110011"when"0100",-4"11011011"when"0101",-5"11011111"when"0110",-6"11110000"when"0111",-7"11111111"when"1000",-8"11111011"when"1001",-9"11110111"when"1010",-A"10011111"when"1011",-B"11001110"when"1100",-C"10111101"when"1101",-D"11001111"when"1110",-E"11000111"when"1111",-F"11111110"when othe