频率计(VHDL语言设计)

1、频率计设计报告学院：班级： 姓名： 学号： 任课教师：频率计的设计 二、设计方案顶层原理图 在顶层原理图中共有5个模块：CNT12、CNT10、CODE 、LOCK 、DECODER三、设计过程（1）、十二进制加法计数器CNT12的VHDL 语言源程序library ieee;port(clk: in std_logic;qq : buffer std_logic_vector(3 downto 0; end cnt12;architecture one of cnt12 is beginprocess(clk beginif (clk'event and clk='1'

2、; then if (qq=11 then qq<="0000" elseqq<=qq+1; end if; end if; end process; end one;（2）十进制加法计数器CNT10的VHDL 语言源程序library ieee;qq :buffer std_logic_vector(3 downto 0; co :out std_logic; end cnt10;architecture one of cnt10 is beginprocess(clk,clr,cs beginif (clr='1' then qq<=&

3、quot;0000"elsif (clk'event and clk='1' then if (cs='1' then if (qq=9 then qq<="0000" elseqq<=qq+1; end if; end if;end if;end process;beginif (qq=9 then co<='0' else co<='1' end if; end process; end;（3）控制模块CODE 的VHDL 语言源程序library ieee;dd

4、: in std_logic_vector(3 downto 0; cs : out std_logic; clr : out std_logic; lock: out std_logic ; end code;architecture one of code is beginprocess(dd beginif (dd=0 then clr<='1' else clr<='0' end if; if (dd=11 then lock<='1' elselock<='0' end if; if ( (dd

5、> 0 and (dd < 9 then cs<='1' else cs<='0' end if; end process; end one;（4）锁存器LOCK 的VHDL 语言源程序library ieee;clk: in std_logic;dd : in std_logic_vector(3 downto 0; qq : out std_logic_vector(3 downto 0 ; end lock;architecture one of lock is beginprocess(clk,dd beginif (clk'event and clk='1' then qq<=dd