实验报告模板

1、同济大学计算机科学与技术系计算机组成原理课程实验报告学号 1452312姓名冯凯专业计算机科学与技术授课老师王力生日 期 实验目标1、熟悉Verilog语言的编写。，计算机2、掌握计算机的每个部件的构成逻辑及工作原理 各部件之间的连接逻辑，计算机整机的工作原理3、掌握CPU功能。4、设计55条单周期指令CPU下板成功2、.在自己的CPU上跑一个汇编程序二、总体设计1. 作品功能设计及原理说明module comp(in put clock, in put reset n, output 2:0 r, output 2:0 g, output 1:0 b, output hs, output v

2、s,);2. 硬件逻辑图三、主要模块设计1.ALUmodule alu（in put 31:0 a,in put 31:0 b,in put 3:0 aluc,output 31:0 r,output zero,/ 零标志output carry, /进位标志位output n egative, /负数标志位output overflow /溢出标志位）;wire 31:0 d_and = a&b;/0100 wire 31:0 d_or = a|b;/0101wire 31:0 d_xor = aAb;/0110wire 31:0 d_nor = (a|b);/0111wire 31

3、:0 dui = b15:0,16'h0;/100xwire 31:0 d_slt = a<b?1:0;wire31:0d_sltu(a31 &&b31 )| (a31 &&b31&&a>b)|(a31&&b31&&a<b);wire 31:0 d_and_or = aluc0?d_or:d_a nd;wire 31:0 d_xor_ nor = aluc0?d_nor:d_xor;wire 31:0 d_a nd_or_xor_ nor = aluc1?d_xor_ nor:d_a nd

4、_or;wire 31:0 d_slt_sltu = aluc0?d_slt:d_sltu;wire 31:0 d_lui_slt_sltu = aluc1?d_slt_sltu:dui;wire 31:0 d_as;wire 31:0 d_sh;wirecarry_as;wiren egative_as;wireoverflow_as;wirecarry_sh;addsub32 as32(a,b,aluc0,aluc1,d_as,carry_as,overflow_as);shift shifter(b,a4:0,aluc1,aluc0,d_sh,carry_sh);mux4x32 sele

5、ct_d(d_as,d_a nd_or_xor_ nor,d_lui_slt_sltu,d_sh,aluc3:2,r);mux4x1 select_carry(carry_as,1'b0,1'b0,carry_sh,aluc3:2,carry);mux4x1 select_overflow(overflow_as,1'b0,1'b0,overflow_sh,aluc3:2,overflow);assig n zero = |r;assig n n egative = r31;en dmoduleHd-iLin 4 /tilhdfl-r U_Lri r2.regf

6、ilemodule regfile(in put 4:0 raddrl,in put 4:0 raddr2,in put 31:0 wdata,in put 4:0 waddr,in put we,in put clk,in put rst,output 31:0 radata1, output 31:0 radata2);reg 31:0 register0:31;assig n radata1=(raddr1=0)?0:registerraddr1;assig n radata2=(raddr2=0)?0:registerraddr2; in teger i;always (posedge

7、 rst or n egedge clk)begi nif(rst=1)beginfor(i=1;i<32;i=i+1)begi n registeri<=0;endendelse begi nregister0<=32'b0;if(waddr!=0)&&we)begi nregisterwaddr<=wdata;endend enden dmodule3.CP0module CoprocessorO(in put clk,in put4:O COadr,in put31:0 C0Wdata,in put C0Write,in put31:0 I

8、n teCause,in put In terrupt,output In teAccept,output31:0 C0State, output reg31:0 C0Data );parameter EPCadr=5'h0;parameter Causeadr=5'h1;parameter Stateadr=5'h2reg31:0 EPC;reg31:0 Cause;reg31:0 State;in itial begi nState <= 32'h1;Cause <= 32'h0;EPC <= 32'h0;end assig

9、 n COState = State;assig n In teAccept =(COWrite && (COadr=Stateadr) && In terrupt && C0Wdata1 |&&(C0Write && (C0adr=Stateadr) && (C0Write(C0adr=Causeadr) && In terrupt && State1;always(posedge clk) begi nif(COWrite) beginif(C0adr=EPCad

10、r) beginEPC <= C0Wdata;if(Interrupt && State1) beginState <= State | 32'b10;Cause <= In teCause;endendif(COadr=Stateadr) beginif(l nterrupt && C0Wdata1) beginState <= COWdata | 32'b10;Cause <= In teCause;endelse begi nState <= C0Wdata;endendif(COadr=Causeadr

11、) begi nCause <= C0Wdata;endendelse begi nif(I nterrupt && State1) beginState <= State | 32'b10;Cause <= In teCause;endendcase(C0adr)EPCadr: beginCOData <= EPC;endCauseadr: beg inCOData <= Cause;endStateadr: begi nCOData <= State;endendcaseenden dmodule4.pc_regmodule pc

12、_reg(in put clk,in put rst,in put 31:0 data_i n,output reg 31:0 data_out);always(posedge clk) begi nif(rst=1)begindata_out<=0;endelse begi ndata_out<=data_i n;endenden dmodule5. mulmodule mul(in put 31:0 a,in put 31:0 b,in put we,input u,/1 有符号，0无符号output 31:0 hi,output 31:0 lo);reg 32:0 a_bi3

13、2:0;in teger i;in teger j;wire 32:0 ai;wire 32:0 bi;wire 65:0乙assign ai = u?a31,a:1'b0,a;assign bi = u?b31,b:1'b0,b;always(*)begi nif(we)for(i = 0;i<32;i = i+1)for(j = 0;j<32;j = j+1)a_bii j = aii&bij;for(i = 0;i<32;i = i+1)a_bii32 = (aii&bi32);for( j = 0;j<32;j = j+1)a_b

14、i32 j = (ai32&bij);a_bi3232 = ai32&bi32;endassig n z =33'b1,a_bi032,a_bi031:0(32'b0,a_bi132,a_bi131:0,1'b031'b0,a_bi232,a_bi231:0,2'b0)(30'b0,a_bi332,a_bi331:0,3'b029'b0,a_bi432,a_bi431:0,4'b0)27'b0,a_bi632,a_bi631:0,6'b0)(26'b0,a_bi732,a_bi731

15、:0,7'b025'b0,a_bi832,a_bi831:0,8'b0)+(24'b0,a_bi932,a_bi931:0,9'b0+23'b0,a_bi1032,a_bi1031:0,10'b0)+(22'b0,a_bi1132,a_bi1131:0,11'b0+21'b0,a_bi1232,a_bi1231:0,12'b0)+(20'b0,a_bi1332,a_bi1331:0,13'b0+19'b0,a_bi1432,a_bi1431:0,14'b0)+(18'

16、b0,a_bi1532,a_bi1531:0,15'b0+17'b0,a_bi1632,a_bi1631:0,16'b0)+(16'b0,a_bi1732,a_bi1731:0,17'b0+15'b0,a_bi1832,a_bi1831:0,18'b0)+(14'b0,a_bi1932,a_bi1931:0,19'b0+13'b0,a_bi2032,a_bi2031:0,20'b0) +(12'b0,a_bi2132,a_bi2131:0,21'b0+11'b0,a_bi2232,a

17、_bi2231:0,22'b0)+(10'b0,a_bi2332,a_bi2331:0,23'b0+9'b0,a_bi2432,a_bi2431:0,24'b0) +(8'b0,a_bi2532,a_bi2531:0,25'b0+7'b0,a_bi2632,a_bi2631:0,26'b0)+(6'b0,a_bi2732,a_bi2731:0,27'b0+(4'b0,a_bi2932,a_bi2931:0,29'b0+3'b0,a_bi3032,a_bi3031:0,30'b

18、0)+(2'b0,a_bi3132,a_bi3131:0,31'b0+1'b1,a_bi3232,a_bi3231:0,32'b0);assig n hi = z63:32;assig n Io = z31:0;en dmodule6.divmodule div(in put 31:0 a1,/被除数低位in put 31:0 a2,/被除数高位in put 31:0 b,/ 除数in put en, 使能in put u,/0 无符号，1有符号output reg 31:0 q,/商output reg 31:0 r/余数)；reg 5:0 cou nt;/3

19、2reg 66:0 a;in itial begi ncoun t=0;endin teger i;always(*)begi nif(en=1) beg inif(u=0)begi na=2'b00,a231:0,a131:0,1'b0;a=a-b31:0,33'b000000000000000000000000000000000;for(i=0;i<32;i=i+1) beginif (a66+a65=2)beg ina0=0;a=a<<1;a=a+b31:0,33'b000000000000000000000000000000000;en

20、delse begi na0=1;a=a<<1;a=a-b31:0,33'b000000000000000000000000000000000;endendif(a66+a65=2)begi na0=0;endelse begi na0=1;endq=a31:0;r=a64:33;endelse begi nif(a231=b31)begi na=2'b00,a231:0,a131:0,1'b0;a=a-b31:0,33'b000000000000000000000000000000000;endelse begi na=2'b00,a231

21、:0,a131:0,1'b0;a=a+b31:0,33'b000000000000000000000000000000000; endfor(i=0;i<32;i=i+1) beginif (a63!=b31)begina0=0;a=a<<1;a=a+b31:0,33'b000000000000000000000000000000000;endelse begi na0=1;a=a<<1;a=a-b31:0,33'b000000000000000000000000000000000;endendif(a64=1)begi na0=0

22、;a=a+b31:0,33'b000000000000000000000000000000000;endelse begi na0=1;endq=a31:0;r=a64:33;endendenden dmodule7.bz0自己设计模块 针对bgez、bgtz、blez、bltz四条指令module bz(in put 31:0 a,in put 1:0 b,output reg z);always(*)beg incase(b)2'b00:/>=0if(a31=0)z <= 1;elsez <= 0;2'b01:/<0if(a31=1)z &l

23、t;= 1;elsez <= 0;2'b10:/<=0if(a31=1|a=0)z <= 1;elsez <= 0;2'b11:/>0if(a31=0|a!=0)z <= 1;elsez <= 0;endcaseenden dmodule8.imemmodule in stmem(in put 31:0 pc,output 31:0 inst);reg 31:0 a 0:255;in itial begi n$readmemh("1.txt",a);endassig n in st = apc31:2;en dmod

24、ule9.dmem/ 因lh、lb、sh、sb等指令对 dmem 做了改动module ram(in put clk,in put ram_e na.in put 1:0 c,0x lw/sw,10 lh/sh,11 lb/hbin put u,in put 31:0 addr,in put 31:0 data_i n,output reg 31:0 data_out);reg 7:0 a 0:20470;always(posedge clk)begi nif(ram_e na)case(c)2'b00:begi naaddr31:2,2'b00 <= data_in7:

25、0;aaddr31:2,2'b00+1 <= data_in15:8;aaddr31:2,2'b00+2 <= data_i n 23:16;aaddr31:2,2'b00+3 <= data_i n 31:24; end2'b10:begi naaddr31:1,1'b0 <= data_i n7:0; aaddr31:1,1'b0+1 <= data_i n15:8; end2'b11:begi naaddr <= datan 7:0;enddefault: beg inaaddr <= 0;

26、endendcaseendalways(*)begi ncase(c)2'b00:begi ndata_out <=aaddr31:2,2'b00+3,aaddr31:2,2'b00+2,aaddr31:2,2'b00+1,aaddr31:2, 2'b00;end2'b01:begi ndata_out <=aaddr31:2,2'b00+3,aaddr31:2,2'b00+2,aaddr31:2,2'b00+1,aaddr31:2, 2'b00;end2'b10:begi ndata_out&

27、lt;=16 u&aaddr31:1,1'b0+17,aaddr31:1,1'b0+1,aaddr31:1,1'b0;end2'b11:begi ndata_out <=24u&aaddr7,aaddr; endendcaseenden dmodule四、应用程序八数码addi $10,$0,1addi $11,$0,2addi $12,$0,3addi $13,$0,4addi $14,$0,5addi $15,$0,6addi $16,$0,7addi $17,$0,8addi $18,$0,0addiu $20,$0,65535add

28、 $21,$0,$0s1:bne $20,$21,s1 add $18,$0,$15addi $15,$0,0add $21,$0,$0s2:addi $21,$21,1bne $20,$21,s2add $15,$0,$14addi $14,$0,0add $21,$0,$0s3:addi $21,$21,1bne $20,$21,s3add $14,$0,$13addi $13,$0,0add $21,$0,$0s4: addi $21,$21,1bne $20,$21,s4add $13,$0,$16addi $16,$0,0add $21,$0,$0s5:addi $21,$21,1b

29、ne $20,$21,s5add $16,$0,$17addi $17,$0,0add $21,$0,$0s6:addi $21,$21,1bne $20,$21,s6add $17,$0,$18add $21,$0,$0 s7:addi $21,$21,1bne $20,$21,s7add $18,$0,$15addi $15,$0,0add $21,$0,$0s8:addi $21,$21,1bne $20,$21,s8add $15,$0,$12addi $12,$0,0add $21,$0,$0s9:addi $21,$21,1bne $20,$21,s9add $12,$0,$11

30、addi $11,$0,0 add $21,$0,$0s10:addi $21,$21,1 bne $20,$21,s10add $11,$0,$14addi $14,$0,0add $21,$0,$0s11:addi $21,$21,1bne $20,$21,s11add $14,$0,$17addi $17,$0,0add $21,$0,$0s12:bne $20,$21,s12 add $17,$0,$16addi $16,$0,0add $21,$0,$0s13:addi $21,$21,1bne $20,$21,s13add $16,$0,$13addi $13,$0,0add $2

31、1,$0,$0s14:addi $21,$21,1 bne $20,$21,s14add $13,$0,$14addi $14,$0,0add $21,$0,$0s15: addi $21,$21,1bne $20,$21,s15add $14,$0,$15addi $15,$0,0add $21,$0,$0s16:addi $21,$21,1bne $20,$21,s16add $15,$0,$18addi $18,$0,0add $21,$0,$0s17:addi $21,$21,1bne $20,$21,s17add $18,$0,$17add $21,$0,$0 s18:addi $2

32、1,$21,1bne $20,$21,s18add $17,$0,$16addi $16,$0,0add $21,$0,$0s19:addi $21,$21,1bne $20,$21,s19add $16,$0,$13addi $13,$0,0add $21,$0,$0s20:addi $21,$21,1bne $20,$21,s20add $13,$0,$14 addi $14,$0,0 add $21,$0,$0s21:addi $21,$21,1bne $20,$21,s21add $14,$0,$11addi $11,$0,0add $21,$0,$0s22:addi $21,$21,

33、1 bne $20,$21,s22add $11,$0,$10addi $10,$0,0add $21,$0,$0en d:sll $0,$0,0j end五、测试/调试过程先测试CPU,每一条指令放入指令寄存器，然后前仿真。前仿真过了看后仿真 延迟，最后分频下板。测试完55条之后，测试斐波那契数列，高斯数列，快速 排序等小应用，都成功通过。之后经过大量时间编写汇编小程序 ，八数码冋题一开始打算手动操作移动 ，但 因为键盘没有写好，用开关的违背了使用CPU的规则而放弃，用A*算法太难， 广度优先算法写好后才发现要开的空间太大，在开发板上跑不动。因此退而求 其次，让机器自己按路径跑出结果。经过大量调试成功。后连接外设VGA,更 改显存。做出小程序。六、实验结果分析3&8-614225?L4236-七、结论计算机进行信息处