verilog数字时钟源程序,分频模块,计时模块,子函数调

1、分频module clkgen (clock,reset,clkdiv,clk500;input clock,reset;output clkdiv;output clk500;reg 31:0 counter1;reg clkdiv;reg clk500;reg 31:0 counter0;/*?1HZ?*/always(posedge clockif(resetbeginclkdiv<=0;counter0<=0;endelse if(counter0=24'd4begincounter0<=0;clkdiv=clkdiv;endelsebegincounter0

2、<=counter0+1;clkdiv<=clkdiv;end/*?500HZ?*/always(posedge clock if(resetbeginclk500<=0;counter1<=0;endelse if(counter1=24'd2begincounter1<=0;clk500=clk500;endelsebegincounter1<=counter1+1;clk500<=clk500;endendmodule计数module jishu24(clkdiv,clear,second,s_carry,minute,m_carry,h

3、our,sL,sH,mL,mH,hL,hH; input clkdiv,clear;output 5:0 second,minute;output 4:0 hour;output s_carry,m_carry;output sL,sH,mL,mH,hL,hH;reg s_carry,m_carry;reg 5:0 second,minute;reg 4:0 hour;reg sL,sH,mL,mH,hL,hH;always(posedge clkdiv or clearif(clearsecond<=0;else if(second!=6'b111011beginsecond&

4、lt;=second+1;s_carry<=0;endelsebeginsecond<=0;s_carry<=1;endalways(posedge s_carry or clearif(clearminute<=0;else if(minute!=6'b111011beginminute<=minute+1;m_carry<=0;endelsebeginminute<=0;m_carry<=1;endalways (posedge m_carry or clearif(clearhour<=0;else if(hour!=5

5、9;b10111beginhour<=hour+1;endelsebeginhour<=0;endalways(posedge secondbeginsL<=second%10;sH<=second/10;endalways(posedge minutebeginmL<=minute%10;mH<=minute/10;endalways(posedge hourbeginhL<=hour%10;hH<=hour/10;endendmodule显示module decode(clk500,reset,hH,hL,mH,mL,sH,sL,HIGH,L

6、OW,COM;input clk500;input reset;input hH,hL;/?input mH,mL;/?input sH,sL;/?output 6:0 HIGH,LOW;/?output 7:0 COM;/?reg 7:0 show_temp_H,show_temp_L;/?reg 7:0 COM;reg 7:0 Uweixuan;/?COM?reg 2:0 sm;/?reg 6:0 HIGH;/?reg 6:0 LOW;/?always(posedge clk500beginif(sm=3'b111sm<=3'b000;elsesm<=sm+3&

7、#39;b001;Uweixuan<=Uweixuan<<1;/?if(Uweixuan=8'b0000_0000Uweixuan<=8'b0000_0001; /?Uweixuan?COM=Uweixuan;/?Uweixuan?endalways(smbegincase(COM8'b1111_1110:show_temp_H=sL;/?8'b1111_1101:show_temp_H=sH;8'b1111_1011:show_temp_H=4'b1010;8'b1111_0111:show_temp_H=mL;

8、8'b1110_1111:show_temp_L=mH;8'b1101_1111:show_temp_L=4'b1010;8'b1011_1111:show_temp_L=hL;8'b0111_1111:show_temp_L=hH;/?endcaseendalways(show_temp_H/?begincase(show_temp_H4'b0000: HIGH=7'b011_1111;4'b0001: HIGH =7'b000_0110;4'b0010: HIGH =7'b101_1011;4'

9、b0011: HIGH =7'b100_1111;4'b0100: HIGH =7'b110_0110;4'b0101: HIGH =7'b110_1101;4'b0110: HIGH =7'b111_1101;4'b0111: HIGH =7'b000_0111;4'b1000: HIGH =7'b111_1111;4'b1001: HIGH =7'b110_1111;4'b1010: HIGH =7'b100_0000;default HIGH =7'b000_0

10、000;endcaseendalways(show_temp_L/?begincase(show_temp_L4'b0000:LOW=7'b011_1111;4'b0001: LOW =7'b000_0110;4'b0010: LOW =7'b101_1011;4'b0011: LOW =7'b100_1111;4'b0100: LOW =7'b110_0110;4'b0101: LOW =7'b110_1101;4'b0110: LOW =7'b111_1101;4'b01

11、11: LOW =7'b000_0111;4'b1000: LOW =7'b111_1111;4'b1001: LOW =7'b110_1111;4'b1010: LOW =7'b100_0000;default LOW =7'b000_0000;endcaseendendmodule主函数实现各函数的调用module main(clock,reset,HIGH,LOW,COM;input clock;input reset;output 6:0 HIGH,LOW;output 7:0 COM;endmodulemodule cl

12、kgen (clock,reset,clkdiv,clk500; input clock,reset;output clkdiv;output clk500;reg 23:0 counter1;reg clkdiv;reg clk500;reg 23:0 counter0;/*?1HZ?*/ always(posedge clockif(resetbeginclkdiv<=0;counter0<=0;endelse if(counter0=24'd4begincounter0<=0;clkdiv=clkdiv;endelsebegincounter0<=coun

13、ter0+1;clkdiv<=clkdiv;end/*?500HZ?*/ always(posedge clock if(resetbeginclk500<=0;counter1<=0;endelse if(counter1=24'd2begincounter1<=0;clk500=clk500;endelsebegincounter1<=counter1+1;clk500<=clk500;endendmodulemodule jishu24(clkdiv,clear,second,s_carry,minute,m_carry,hour,sL,sH,

14、mL,mH,hL,hH; input clkdiv,clear;output 5:0 second,minute;output 4:0 hour;output s_carry,m_carry;output sL,sH,mL,mH,hL,hH;reg s_carry,m_carry;reg 5:0 second,minute;reg 4:0 hour;reg sL,sH,mL,mH,hL,hH;always(posedge clkdiv or clearif(clearsecond<=0;else if(second!=6'b111011beginsecond<=second

15、+1;s_carry<=0;endelsebeginsecond<=0;s_carry<=1;endalways(posedge s_carry or clearif(clearminute<=0;else if(minute!=6'b111011beginminute<=minute+1;m_carry<=0;endelsebeginminute<=0;m_carry<=1;endalways (posedge m_carry or clearif(clearhour<=0;else if(hour!=5'b10111be

16、ginhour<=hour+1;endelsebeginhour<=0;endalways(posedge secondbeginsL<=second%10;sH<=second/10;endalways(posedge minutebeginmL<=minute%10;mH<=minute/10;endalways(posedge hourbeginhL<=hour%10;hH<=hour/10;endendmodulemodule shumaguan(clk500,reset1,hH,hL,mH,mL,sH,sL,HIGH,LOW,COM;i

17、nput clk500;input reset1;input hH,hL;/?input mH,mL;/?input sH,sL;/?output 6:0 HIGH,LOW;/?output 7:0 COM;/?reg 7:0 show_temp_H,show_temp_L;/?reg 7:0 COM;reg 7:0 Uweixuan;/?COM?reg 2:0 sm;/?reg 6:0 HIGH;/?reg 6:0 LOW;/?always(posedge clk500beginif(sm=3'b111sm<=3'b000;elsesm<=sm+3'b00

18、1;Uweixuan<=Uweixuan<<1;if(Uweixuan=8'b0000_0000Uweixuan<=8'b0000_0001; /?Uweixuan? COM=Uweixuan;/?Uweixuan?endalways(clk500begincase(COM8'b1111_1110:show_temp_H=sL;/?8'b1111_1101:show_temp_H=sH;8'b1111_1011:show_temp_H=4'b1010;8'b1111_0111:show_temp_H=mL;8

19、9;b1110_1111:show_temp_L=mH;8'b1101_1111:show_temp_L=4'b1010;8'b1011_1111:show_temp_L=hL;8'b0111_1111:show_temp_L=hH;/?endcaseendalways(show_temp_H/?begincase(show_temp_H4'b0000: HIGH=7'b011_1111;4'b0001: HIGH =7'b000_0110;4'b0010: HIGH =7'b101_1011;4'b001

20、1: HIGH =7'b100_1111;4'b0100: HIGH =7'b110_0110;4'b0101: HIGH =7'b110_1101;4'b0110: HIGH =7'b111_1101;4'b0111: HIGH =7'b000_0111;4'b1000: HIGH =7'b111_1111;4'b1001: HIGH =7'b110_1111;4'b1010: HIGH =7'b100_0000;default HIGH =7'b000_0000;

21、 endcaseendalways(show_temp_L/?begincase(show_temp_L4'b0000: LOW =7'b011_1111;4'b0001: LOW =7'b000_0110;4'b0010: LOW =7'b101_1011;4'b0011: LOW =7'b100_1111;4'b0100: LOW =7'b110_0110;4'b0101: LOW =7'b110_1101;4'b0110: LOW =7'b111_1101;4'b0111: LOW =7'b000_0111;4'b1000: LOW =7'b111_1111;4'b1