verilog编写的基本电路逻辑与仿真

1、集成电路与Verilog 语言实验1：分别用门级建模、数据流级建模、和行为级建模实现一个2选1的MUX ，两个输入端分别为A 和B ，当选择端SEL=0时，输出F 选择A ；当选择端SEL=1时，输出F 选择 门级建模： 源代码：/MUX2to1 gatelevelmodule MUX_gate(a,b,sel,f; input a; input b; input sel; output f; reg f;wire nsel,y1,y2; not unot(nsel,sel; and u1and(y1,a,nsel; and u2and(y2,b,sel; or uor(f,y1,y2; en

2、dmoduleTB 代码：module tb_MUX_gate; / Inputs reg a; reg b; reg sel;第2页 共15页/ Outputs wire f;/ Instantiate the Unit Under Test (UUT MUX_gate uut ( .a(a, .b(b, .sel(sel, .f(f ;initial begin/ Initialize Inputs a = 0; b = 0; sel = 0;/ Wait 100 ns for global reset to finish #10/ Add stimulus here a=1; b=0;

3、sel=0; #10; a=1; b=0; sel=1; #10;#10$finish; end endmodule 数据流级建模： 源代码：/MUX2to1 datapromodule MUX_datapro(a,b,sel,f;input a; input b; input sel; output f;reg f;wire nsel,y1,y2; assign nsel=sel; assign y1=a&nsel; assign y2=b&sel;第3页 共15页assign f=y1|y2; endmodule TB 代码：module tb_MUX_datarpro;

4、/ Inputs reg a; reg b; reg sel; / Outputs wire f;/ Instantiate the Unit Under Test (UUT MUX_datapro uut ( .a(a, .b(b, .sel(sel, .f(f ;initial begin/ Initialize Inputs a = 0; b = 0; sel = 0;/ Wait 100 ns for global reset to finish #10;/ Add stimulus here a=1; b=0; sel=0; #10; a=1; b=0; sel=1; #10;#10

5、$finish; en endmodule第4页 共15页行为级建模： 源代码：/MUX2to1 behavmodule MUX_behav(f,a,b,sel; input a,b,sel; output f; reg f;reg y1,y2,nsel;always (a or b or sel beginnsel <=sel; y1 <= a&nsel; y2 <= b&sel; f <= y1|y2; endendmodule TB 代码：module tb_MUX_behav; / Inputs reg a; reg b; reg sel; /

6、Outputs wire f;/ Instantiate the Unit Under Test (UUT MUX_behav uut ( .a(a, .b(b, .sel(sel,第5页 共15页 .f(f;initial begin/ Initialize Inputsa = 0;b = 0;sel = 0;/ Wait 100 ns for global reset to finish#10;/ Add stimulus herea=1;b=0;sel=0;#10;a=1;b=0;sel=1;#10;#10$finish;endendmodule 实验2题目：实现一个计数器，计数时计数器

7、可从0计到10。源代码：module counter(din,up1_down0,clk,nrst,sta1_pau0,load,counter;input3:0 din;input up1_down0;input clk;input nrst;input sta1_pau0;input load;output 3:0 counter;reg 3:0 counter;always (posedge clk or negedge nrstbeginif(nrstcounter <= 4'b0000;else if(loadcounter <= din;elsebeginif(

8、sta1_pau0counter <= counter;第6页 共15页elseif(up1_down0if (counter = 10counter <= 4'b0000;elsecounter <= counter + 1;elseif (counter = 0counter <= 4'b1010;elsecounter <= counter - 1;endendendmodule TB 代码：module tb2;/ Inputsreg 3:0 din;reg up1_down0;reg clk;reg nrst;reg sta1_pau0;

9、reg load;/ Outputswire 3:0 counter;/ Instantiate the Unit Under Test (UUTcounter uut (.din(din,.up1_down0(up1_down0,.clk(clk,.nrst(nrst,.sta1_pau0(sta1_pau0,.load(load,.counter(counter第7页 共15页;initialclk = 1'b0;always#5 clk = clk;initial begin/ Initialize Inputsdin = 0;up1_down0 = 0;nrst = 0;sta

10、1_pau0 = 0;load = 0;/ Wait 100 ns for global reset to finish#50;/ Add stimulus here/从0开始加计数din = 4'b0111;nrst = 1;up1_down0 = 1;sta1_pau0 = 1;#210;/暂停sta1_pau0 = 0;#20;/从7开始减计数load = 1;#10;load = 0;sta1_pau0 = 1;up1_down0 = 0;#200;#20 $finish;endendmodule仿真结果： 第8页 共15页实验3题目：由Morre 状态机设计一个简单的交通灯，

11、假定红灯时间为9个时间单位，绿灯时间为6个时间单位，黄灯时间为3个时间单位。源代码：module light_machine(clk,nrst,y,t;input clk;input nrst;output 1:0 y;output 3:0 t;reg 3:0 q;reg 1:0 y;reg 1:0 state;reg 3:0 t;parameter green = 2'b00,yellow = 2'b01,red = 2'b11;initialbeginq <= 4'b0;t <= 4'b0;endalways (posedge clk o

12、r negedge nrstbeginif(!nrstbeginstate <= green;y <= 2'bz;endelsecase(stategreen:beginq <= q +1;t <= q;if(q = 5beginq <= 4'b0;state <= yellow;endelsebeginy <= 2'b00;state <= green;endendyellow:beginq <= q +1;t <= q;if (q = 2beginq <= 4'b0;state <= r

13、ed;endelse第9页 共15页beginy <= 2'b01;state <= yellow;end endred:beginq <= q + 1;t <= q;if (q = 8beginq <= 4'b0; state <= green;endelsebeginy <= 2'b11;state <= red;endendendcaseendendmodule TB 代码：module tb_2;/ Inputsreg clk;reg nrst;/ Outputswire 1:0 y;wire 3:0 t;/ In

14、stantiate the Unit Under Test (UUT light_machine uut (.clk(clk,.nrst(nrst,.y(y,.t(t第10页 共15页集成电路与verilog 语言实验报告;initialclk = 1'b0;always#5 clk = clk;initial begin/ Initialize Inputsnrst = 0;/ Wait 100 ns for global reset to finish#30;/ Add stimulus herenrst = 1;#500;#20$finish;endendmodule 实验4题目

15、：对一个400MHz 的时钟分别完成2、4、8分频。源代码：module divclk(clkin,nrst,din, clkout;input clkin;input nrst;input 1:0 din;output clkout;reg 28:0 q;reg clkout;initialbeginq <=29'b0;endalways (posedge clkin or negedge nrstbeginif(nrstq <= 29'b0;集成电路与 verilog 语言实验报告elseq <= q + 29'b1;endalways (pose

16、dge clkinbegincase(din2'b00:clkout <= q0;2'b01:clkout <= q1;2'b10:clkout <= q2;default:clkout <= 1'bz;endcaseendendmoduleTB 文件：module tb_div;/ Inputsreg clkin;reg nrst;reg 1:0 din;/ Outputswire clkout;/ Instantiate the Unit Under Test (UUTdivclk uut (.clkin(clkin,.nrst(nr

17、st,.din(din,.clkout(clkout;initial clkin = 1'b0;always#1.25 clkin = clkin;initial begin/ Initialize Inputsnrst = 0;din = 2'b11;/ Wait 100 ns for global reset to finish#50;/ Add stimulus herenrst = 1;din = 2'b00;#50;din = 2'b01;#50;din = 2'b10;#50;din = 2'b11;#50;#20$finish;en

18、dendmodule 实验5题目：按照病情严重程度将8名病人分配到8个病房，1号病房病情最轻，8号病房病人病情最严重。每个病房有一个按钮用于呼叫医生，在医生办公室有个显示屏，用于显示哪个病房按了按钮。由于病情不同，要求当病情较严重的病房按了按钮后，医生办公室的显示屏要优先显示其病房号。源代码：module priority_encoder(clk,I0,I1,I2,I3,I4,I5,I6,I7,Y;input clk;input I0;input I1;input I2;input I3;input I4;input I5;input I6;input I7;output 2:0 Y;reg 2:0 Y;always (posedge clk beginif(I7Y <= 3'b111;else if(I6Y <= 3'b110;else if(I5Y <= 3'b101;else if(I4Y <= 3'b100;else if(I3Y <= 3'b011;else if(I2Y <= 3'b010;else if(I1Y <= 3'b001;else if(I0Y <= 3'b000;elseY <=