DSP与FPGA间简单通信(EMIF)

1、精选优质文档-倾情为你奉上DSP与FPGA间简单通信 DSP与FPGA采用EMIF接口通信，即将FPGA作为DSP的外部SRAM，只需设置EMIF控制的存储器为SRAM类型即可，DSP通过EMIF接口读写SRAM的时序如下: 参考datasheettms320dm642.pdf 可以根据以上时序图编写FPGA代码，以下仅供参考：module DSP_FPGA(                  &

2、#160;                                                 &

3、#160;   input clk,                                             &#

4、160;               input 2:0 addr,       /简单测试，没有用到所有地址                               

5、0;              inout 15:0 data,     /16位数据宽度                                  &

6、#160;           input CE_2,/FPGA片选                                    

7、              input AOE,                                   &

8、#160;                         input AWE                       

9、60;                                   );               

10、                                                  

11、                                                          &#

12、160;                                      reg 15:0 DSP_FPGA_REG0;       

13、60;                  reg 15:0 DSP_FPGA_REG1;                           

14、0;  reg 15:0 DSP_FPGA_REG2;                          reg 15:0 DSP_FPGA_REG3;              

15、            reg 15:0 DSP_FPGA_REG4;                              reg 15:0 DSP_FPGA_REG5;&#

16、160;                         reg 15:0 DSP_FPGA_REG6;                    

17、60;     reg 15:0 DSP_FPGA_REG7;                                        

18、0;                                        wire rd_en = CE_2 && AOE;reg 15:0 data_reg; &

19、#160;    /always (posedge clk) /DSP读操作,The sampling point of DSP reading is the risging edge of AWE!                              

20、 always (*)    /这里没有用时钟，用的latchbegin                                        

21、;           if(rd_en)                                      begin&

22、#160;                                                 

23、case(addr2:0)                                       3'd0   :  data_reg <= DSP_FPGA_REG0;

24、           3'd1   :  data_reg <= DSP_FPGA_REG1;           3'd2   :  data_reg <= DSP_FPGA_REG2;           3

25、'd3   :  data_reg <= DSP_FPGA_REG3;           3'd4   :  data_reg <= DSP_FPGA_REG4;           3'd5   :  data_reg <= DSP_FPGA_REG5; 

26、;          3'd6   :  data_reg <= DSP_FPGA_REG6;           3'd7   :  data_reg <= DSP_FPGA_REG7;           &

27、#160;    default:  ;                                         endcase   

28、;                                     end              

29、                                                   

30、;                               end                  &#

31、160;                                       reg AWE_tmp1;reg AWE_tmp2;always (posedge clk)begin  

32、0;  AWE_tmp1 <= AWE;     AWE_tmp2 <= AWE_tmp1;end            wire AWE_RISING = AWE_tmp2 && AWE_tmp1;/与clk同步       always (*)        

33、;                           begin                      

34、                    if(AWE_RISING)      /这里也没有用时钟，用的是latch                   

35、60;        begin                                         

36、60;  case(addr2:0)                                3'd0   :  DSP_FPGA_REG0 <= data;      

37、    3'd1   :  DSP_FPGA_REG1 <= data;          3'd2   :  DSP_FPGA_REG2 <= data;          3'd3   :  DSP_FPGA_REG3 <= data; 

38、60;        3'd4   :  DSP_FPGA_REG4 <= data;          3'd5   :  DSP_FPGA_REG5 <= data;          3'd6   :  DSP_FPG

39、A_REG6 <= data;          3'd7   :  DSP_FPGA_REG7 <= data;             default:  ;              

40、                    endcase                               &#

41、160; end                                      end          &

42、#160;                              assign data =  rd_en ? data_reg : 16'hzzzz;      endmodule/DSP(具体为DM642)端程序：

43、寄存器设置参考 EMIF Reference Guide- spru266b.pdf 即spru266#define   FPGA_ADDR              0xA  /#define   EMIFA_GBLCTL         0x#define   EMIFA_CECTL2         0x /#define   EMIFA_CESEC2         0x  void  delay(unsigned long time)&