vhdl红绿灯实验

1、南北方向和东西方向的共六个颜色灯（红、黄、绿）按给定延迟时间循环点亮。东西方向通行30秒，南北方向通行30秒。选用2个七段码显示时间，进行倒计时。当时间到后，进行红黄绿灯显示切换。交通灯控制器的4个状态南北公路东西公路状态0 25秒绿红状态1 5秒红灯红+黄状态2 25秒红绿状态3 5秒红+黄红交通灯控制器的状态转换图library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity traffic_signal_light is port (clk:instd_logic;clr:instd_logi

2、c;rst:instd_logic; dig_sel_n:out std_logic_vector(7 downto 0);ewsn : out std_logic_vector(5 downto 0);dat_out:out std_logic_vector(7 downto 0);useless : out std_logic_vector(5 downto 0);end entity traffic_signal_light;architecture bhv of traffic_signal_light istype states is (S0,S1,S2,S3);signal cur

3、rent_state,next_state : states := S0; signal dig0,dig1,dig2,dig3 : std_logic_vector(7 downto 0);signal digSelectAddress : integer range 0 to 3;-当前将要显示数码管的地址控制线； signal data1: integer range 40 downto 0 ; -data => 送显示的时钟数字信号；signal data2 : integer range 40 downto 0 ;signal clock_1s : std_logic;sign

4、al clock_5ms: std_logic;-数码管的译码函数- - 形参 data :为要译码的数字，范围为：09； - 返回值 ledSegment :为译码好的七段数码管断码；function decode( data: integer range 0 to 9 )return std_logic_vector isvariable ledSegment: std_logic_vector(7 downto 0);beginCASE data ISWHEN 0 =>ledSegment := "11000000"- 0xC0;0 WHEN 1 =>le

5、dSegment := "11111001"- 0xf9;1WHEN 2 =>ledSegment := "10100100"- 0xa4;2WHEN 3 =>ledSegment := "10110000"- 0xb0 3WHEN 4 =>ledSegment := "10011001"- 0x99 4WHEN 5 =>ledSegment := "10010010"- 0x92;5WHEN 6 =>ledSegment := "10000010&quo

6、t;- ox82;6WHEN 7 =>ledSegment := "11111000"- 0xf8;7WHEN 8 =>ledSegment := "10000000"- 0x80;8WHEN 9 =>ledSegment := "10010000"- 0x90;9WHEN OTHERS =>null; END CASE; return ledSegment;end decode;-begin -architecture useless <= "111111"dig1 <= de

7、code(data1 /10 rem 10);dig0 <= decode(data1 rem 10 );dig3 <= decode(data2 /10 rem 10);dig2 <= decode(data2 rem 10 ); -状态转换-Change_state : process(current_state) begin case current_state is when S0 => ewsn <= "110011"-rgif(data1 = 1 ) then next_state <= S1 ;else next_state

8、 <= S0 ;end if ;when S1 => ewsn <= "101011"-ryif(data1 = 1 ) then next_state <= S2 ;else next_state <= S1 ;end if ;when S2 => ewsn <= "011110"if( data1 = 5 ) then next_state <= S3 ;else next_state <= S2 ;end if ;when S3 => ewsn <= "011101&quo

9、t;if( data1 = 1 ) then next_state <= S0 ;else next_state <= S3 ;end if ;end case ;end process Change_state;-时序进程-Reg : process(clock_1s,rst)beginif rst = '1' then current_state <= S0;elsif (clock_1s = '1' and clock_1s'event) thencurrent_state <= next_state;end if; end

10、 process Reg; -分频器输出1s时钟给数码管的定时器-Div_clock_1s : process(clk) variable count :integer range 0 to 20_000_000 ;beginif(clk = '1' and clk'event) thenif count = 19_999_999 thencount:= 0;elsecount:= count +1;end if;if(count>= 10_000_000) thenclock_1s <= '0'elseclock_1s <= '

11、;1'end if;end if; end process Div_clock_1s; -25秒和5秒倒计时- -东西红路灯数码管倒计时- counter1 : process(clock_1s) variable data_60second : integer range 60 downto 1 ; begin if(clock_1s'event and clock_1s = '1')thenif( data1 = 0 ) thendata_60second := 60;data1 <= 25;else data_60second := data_60s

12、econd - 1; if( data_60second > 35 ) thendata1 <= ( data_60second - 35 ) ;else if(data_60second > 30) thendata1 <= (data_60second - 30 ) ;elsedata1 <= data_60second;end if;end if;end if;end if;end process counter1; -南北红路灯数码管倒计时- counter2 : process(clock_1s) variable data_60second : int

13、eger range 60 downto 1 ; begin if(clock_1s'event and clock_1s = '1')thenif( data2 = 0 ) thendata_60second := 60;data2 <= 30;else data_60second := data_60second - 1;if( data_60second > 30 ) thendata2 <= ( data_60second - 30 ) ;else if(data_60second > 5) thendata2 <= (data_6

14、0second - 5 ) ;else data2 <= data_60second;end if; end if;end if;end if;end process counter2; -数码管刷新频率产生进程-Div_clock_5ms : process(clk) variable count :integer range 0 to 100_000 ;beginif(clk = '1' and clk'event) thenif count = 99_999 thencount:= 0;elsecount:= count +1;end if;if(count

15、>= 50_000) thenclock_5ms <= '0'elseclock_5ms <= '1'end if;end if; end process Div_clock_5ms;-counter3 : process(clock_5ms) beginif(clock_5ms = '1' and clock_5ms'event) thenif digSelectAddress = 3 thendigSelectAddress <= 0;elsedigSelectAddress <= digSelectAddress + 1;end if;end if; end process counter3;- show : process(digSelectAddress) begincase digSelectAddress iswhen 0 => dig_sel_n <= "11111110"dat_out <= dig0;w